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1 /*
2 * Copyright (c) 2000-2010 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /*
32 * Mach Operating System
33 * Copyright (c) 1991,1990,1989,1988 Carnegie Mellon University
34 * All Rights Reserved.
35 *
36 * Permission to use, copy, modify and distribute this software and its
37 * documentation is hereby granted, provided that both the copyright
38 * notice and this permission notice appear in all copies of the
39 * software, derivative works or modified versions, and any portions
40 * thereof, and that both notices appear in supporting documentation.
41 *
42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
45 *
46 * Carnegie Mellon requests users of this software to return to
47 *
48 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
49 * School of Computer Science
50 * Carnegie Mellon University
51 * Pittsburgh PA 15213-3890
52 *
53 * any improvements or extensions that they make and grant Carnegie Mellon
54 * the rights to redistribute these changes.
55 */
56 /*
57 */
58
59 /*
60 * Hardware trap/fault handler.
61 */
62
63 #include <mach_kdp.h>
64 #include <mach_ldebug.h>
65
66 #include <types.h>
67 #include <i386/eflags.h>
68 #include <i386/trap.h>
69 #include <i386/pmap.h>
70 #include <i386/fpu.h>
71 #include <i386/misc_protos.h> /* panic_io_port_read() */
72 #include <i386/lapic.h>
73
74 #include <mach/exception.h>
75 #include <mach/kern_return.h>
76 #include <mach/vm_param.h>
77 #include <mach/i386/thread_status.h>
78
79 #include <vm/vm_kern.h>
80 #include <vm/vm_fault.h>
81
82 #include <kern/kern_types.h>
83 #include <kern/processor.h>
84 #include <kern/thread.h>
85 #include <kern/task.h>
86 #include <kern/sched.h>
87 #include <kern/sched_prim.h>
88 #include <kern/exception.h>
89 #include <kern/spl.h>
90 #include <kern/misc_protos.h>
91 #include <kern/debug.h>
92
93 #include <sys/kdebug.h>
94
95 #include <string.h>
96
97 #include <i386/postcode.h>
98 #include <i386/mp_desc.h>
99 #include <i386/proc_reg.h>
100 #if CONFIG_MCA
101 #include <i386/machine_check.h>
102 #endif
103 #include <mach/i386/syscall_sw.h>
104
105 #include <libkern/OSDebug.h>
106
107 #include <machine/pal_routines.h>
108
109 extern void throttle_lowpri_io(int);
110 extern void kprint_state(x86_saved_state64_t *saved_state);
111
112 /*
113 * Forward declarations
114 */
115 static void user_page_fault_continue(kern_return_t kret);
116 #ifdef __i386__
117 static void panic_trap(x86_saved_state32_t *saved_state);
118 static void set_recovery_ip(x86_saved_state32_t *saved_state, vm_offset_t ip);
119 extern void panic_64(x86_saved_state_t *, int, const char *, boolean_t);
120 #else
121 static void panic_trap(x86_saved_state64_t *saved_state);
122 static void set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip);
123 #endif
124
125 volatile perfCallback perfTrapHook = NULL; /* Pointer to CHUD trap hook routine */
126
127 #if CONFIG_DTRACE
128 /* See <rdar://problem/4613924> */
129 perfCallback tempDTraceTrapHook = NULL; /* Pointer to DTrace fbt trap hook routine */
130
131 extern boolean_t dtrace_tally_fault(user_addr_t);
132 #endif
133
134 extern boolean_t pmap_smep_enabled;
135
136 void
137 thread_syscall_return(
138 kern_return_t ret)
139 {
140 thread_t thr_act = current_thread();
141 boolean_t is_mach;
142 int code;
143
144 pal_register_cache_state(thr_act, DIRTY);
145
146 if (thread_is_64bit(thr_act)) {
147 x86_saved_state64_t *regs;
148
149 regs = USER_REGS64(thr_act);
150
151 code = (int) (regs->rax & SYSCALL_NUMBER_MASK);
152 is_mach = (regs->rax & SYSCALL_CLASS_MASK)
153 == (SYSCALL_CLASS_MACH << SYSCALL_CLASS_SHIFT);
154 if (kdebug_enable && is_mach) {
155 /* Mach trap */
156 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
157 MACHDBG_CODE(DBG_MACH_EXCP_SC,code)|DBG_FUNC_END,
158 ret, 0, 0, 0, 0);
159 }
160 regs->rax = ret;
161 #if DEBUG
162 if (is_mach)
163 DEBUG_KPRINT_SYSCALL_MACH(
164 "thread_syscall_return: 64-bit mach ret=%u\n",
165 ret);
166 else
167 DEBUG_KPRINT_SYSCALL_UNIX(
168 "thread_syscall_return: 64-bit unix ret=%u\n",
169 ret);
170 #endif
171 } else {
172 x86_saved_state32_t *regs;
173
174 regs = USER_REGS32(thr_act);
175
176 code = ((int) regs->eax);
177 is_mach = (code < 0);
178 if (kdebug_enable && is_mach) {
179 /* Mach trap */
180 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
181 MACHDBG_CODE(DBG_MACH_EXCP_SC,-code)|DBG_FUNC_END,
182 ret, 0, 0, 0, 0);
183 }
184 regs->eax = ret;
185 #if DEBUG
186 if (is_mach)
187 DEBUG_KPRINT_SYSCALL_MACH(
188 "thread_syscall_return: 32-bit mach ret=%u\n",
189 ret);
190 else
191 DEBUG_KPRINT_SYSCALL_UNIX(
192 "thread_syscall_return: 32-bit unix ret=%u\n",
193 ret);
194 #endif
195 }
196 throttle_lowpri_io(TRUE);
197
198 thread_exception_return();
199 /*NOTREACHED*/
200 }
201
202
203 static inline void
204 user_page_fault_continue(
205 kern_return_t kr)
206 {
207 thread_t thread = current_thread();
208 user_addr_t vaddr;
209
210 if (thread_is_64bit(thread)) {
211 x86_saved_state64_t *uregs;
212
213 uregs = USER_REGS64(thread);
214
215 vaddr = (user_addr_t)uregs->cr2;
216 } else {
217 x86_saved_state32_t *uregs;
218
219 uregs = USER_REGS32(thread);
220
221 vaddr = uregs->cr2;
222 }
223
224 if (__probable((kr == KERN_SUCCESS) || (kr == KERN_ABORTED))) {
225 thread_exception_return();
226 /*NOTREACHED*/
227 }
228
229 /* PAL debug hook */
230 pal_dbg_page_fault( thread, vaddr, kr );
231
232 i386_exception(EXC_BAD_ACCESS, kr, vaddr);
233 /*NOTREACHED*/
234 }
235
236 /*
237 * Fault recovery in copyin/copyout routines.
238 */
239 struct recovery {
240 uintptr_t fault_addr;
241 uintptr_t recover_addr;
242 };
243
244 extern struct recovery recover_table[];
245 extern struct recovery recover_table_end[];
246
247 const char * trap_type[] = {TRAP_NAMES};
248 unsigned TRAP_TYPES = sizeof(trap_type)/sizeof(trap_type[0]);
249
250 extern void PE_incoming_interrupt(int interrupt);
251
252 #if defined(__x86_64__) && DEBUG
253 void
254 kprint_state(x86_saved_state64_t *saved_state)
255 {
256 kprintf("current_cpu_datap() 0x%lx\n", (uintptr_t)current_cpu_datap());
257 kprintf("Current GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_GS_BASE));
258 kprintf("Kernel GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_KERNEL_GS_BASE));
259 kprintf("state at 0x%lx:\n", (uintptr_t) saved_state);
260
261 kprintf(" rdi 0x%llx\n", saved_state->rdi);
262 kprintf(" rsi 0x%llx\n", saved_state->rsi);
263 kprintf(" rdx 0x%llx\n", saved_state->rdx);
264 kprintf(" r10 0x%llx\n", saved_state->r10);
265 kprintf(" r8 0x%llx\n", saved_state->r8);
266 kprintf(" r9 0x%llx\n", saved_state->r9);
267 kprintf(" v_arg6 0x%llx\n", saved_state->v_arg6);
268 kprintf(" v_arg7 0x%llx\n", saved_state->v_arg7);
269 kprintf(" v_arg8 0x%llx\n", saved_state->v_arg8);
270
271 kprintf(" cr2 0x%llx\n", saved_state->cr2);
272 kprintf("real cr2 0x%lx\n", get_cr2());
273 kprintf(" r15 0x%llx\n", saved_state->r15);
274 kprintf(" r14 0x%llx\n", saved_state->r14);
275 kprintf(" r13 0x%llx\n", saved_state->r13);
276 kprintf(" r12 0x%llx\n", saved_state->r12);
277 kprintf(" r11 0x%llx\n", saved_state->r11);
278 kprintf(" rbp 0x%llx\n", saved_state->rbp);
279 kprintf(" rbx 0x%llx\n", saved_state->rbx);
280 kprintf(" rcx 0x%llx\n", saved_state->rcx);
281 kprintf(" rax 0x%llx\n", saved_state->rax);
282
283 kprintf(" gs 0x%x\n", saved_state->gs);
284 kprintf(" fs 0x%x\n", saved_state->fs);
285
286 kprintf(" isf.trapno 0x%x\n", saved_state->isf.trapno);
287 kprintf(" isf._pad 0x%x\n", saved_state->isf._pad);
288 kprintf(" isf.trapfn 0x%llx\n", saved_state->isf.trapfn);
289 kprintf(" isf.err 0x%llx\n", saved_state->isf.err);
290 kprintf(" isf.rip 0x%llx\n", saved_state->isf.rip);
291 kprintf(" isf.cs 0x%llx\n", saved_state->isf.cs);
292 kprintf(" isf.rflags 0x%llx\n", saved_state->isf.rflags);
293 kprintf(" isf.rsp 0x%llx\n", saved_state->isf.rsp);
294 kprintf(" isf.ss 0x%llx\n", saved_state->isf.ss);
295 }
296 #endif
297
298
299 /*
300 * Non-zero indicates latency assert is enabled and capped at valued
301 * absolute time units.
302 */
303
304 uint64_t interrupt_latency_cap = 0;
305 boolean_t ilat_assert = FALSE;
306
307 void
308 interrupt_latency_tracker_setup(void) {
309 uint32_t ilat_cap_us;
310 if (PE_parse_boot_argn("interrupt_latency_cap_us", &ilat_cap_us, sizeof(ilat_cap_us))) {
311 interrupt_latency_cap = ilat_cap_us * NSEC_PER_USEC;
312 nanoseconds_to_absolutetime(interrupt_latency_cap, &interrupt_latency_cap);
313 } else {
314 interrupt_latency_cap = LockTimeOut;
315 }
316 PE_parse_boot_argn("-interrupt_latency_assert_enable", &ilat_assert, sizeof(ilat_assert));
317 }
318
319 void interrupt_reset_latency_stats(void) {
320 uint32_t i;
321 for (i = 0; i < real_ncpus; i++) {
322 cpu_data_ptr[i]->cpu_max_observed_int_latency =
323 cpu_data_ptr[i]->cpu_max_observed_int_latency_vector = 0;
324 }
325 }
326
327 void interrupt_populate_latency_stats(char *buf, unsigned bufsize) {
328 uint32_t i, tcpu = ~0;
329 uint64_t cur_max = 0;
330
331 for (i = 0; i < real_ncpus; i++) {
332 if (cur_max < cpu_data_ptr[i]->cpu_max_observed_int_latency) {
333 cur_max = cpu_data_ptr[i]->cpu_max_observed_int_latency;
334 tcpu = i;
335 }
336 }
337
338 if (tcpu < real_ncpus)
339 snprintf(buf, bufsize, "0x%x 0x%x 0x%llx", tcpu, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency_vector, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency);
340 }
341
342 /*
343 * Handle interrupts:
344 * - local APIC interrupts (IPIs, timers, etc) are handled by the kernel,
345 * - device interrupts go to the platform expert.
346 */
347 void
348 interrupt(x86_saved_state_t *state)
349 {
350 uint64_t rip;
351 uint64_t rsp;
352 int interrupt_num;
353 boolean_t user_mode = FALSE;
354 int ipl;
355 int cnum = cpu_number();
356 int itype = 0;
357
358 if (is_saved_state64(state) == TRUE) {
359 x86_saved_state64_t *state64;
360
361 state64 = saved_state64(state);
362 rip = state64->isf.rip;
363 rsp = state64->isf.rsp;
364 interrupt_num = state64->isf.trapno;
365 #ifdef __x86_64__
366 if(state64->isf.cs & 0x03)
367 #endif
368 user_mode = TRUE;
369 } else {
370 x86_saved_state32_t *state32;
371
372 state32 = saved_state32(state);
373 if (state32->cs & 0x03)
374 user_mode = TRUE;
375 rip = state32->eip;
376 rsp = state32->uesp;
377 interrupt_num = state32->trapno;
378 }
379
380 if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_INTERPROCESSOR_INTERRUPT))
381 itype = 1;
382 else if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_TIMER_INTERRUPT))
383 itype = 2;
384 else
385 itype = 3;
386
387 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
388 MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_START,
389 interrupt_num,
390 (user_mode ? rip : VM_KERNEL_UNSLIDE(rip)),
391 user_mode, itype, 0);
392
393 SCHED_STATS_INTERRUPT(current_processor());
394
395 ipl = get_preemption_level();
396
397 /*
398 * Handle local APIC interrupts
399 * else call platform expert for devices.
400 */
401 if (!lapic_interrupt(interrupt_num, state))
402 PE_incoming_interrupt(interrupt_num);
403
404 if (__improbable(get_preemption_level() != ipl)) {
405 panic("Preemption level altered by interrupt vector 0x%x: initial 0x%x, final: 0x%x\n", interrupt_num, ipl, get_preemption_level());
406 }
407
408
409 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
410 MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_END,
411 interrupt_num, 0, 0, 0, 0);
412
413 if (cpu_data_ptr[cnum]->cpu_nested_istack) {
414 cpu_data_ptr[cnum]->cpu_nested_istack_events++;
415 }
416 else {
417 uint64_t int_latency = mach_absolute_time() - cpu_data_ptr[cnum]->cpu_int_event_time;
418 if (ilat_assert && (int_latency > interrupt_latency_cap) && !machine_timeout_suspended()) {
419 panic("Interrupt vector 0x%x exceeded interrupt latency threshold, 0x%llx absolute time delta, prior signals: 0x%x, current signals: 0x%x", interrupt_num, int_latency, cpu_data_ptr[cnum]->cpu_prior_signals, cpu_data_ptr[cnum]->cpu_signals);
420 }
421 if (int_latency > cpu_data_ptr[cnum]->cpu_max_observed_int_latency) {
422 cpu_data_ptr[cnum]->cpu_max_observed_int_latency = int_latency;
423 cpu_data_ptr[cnum]->cpu_max_observed_int_latency_vector = interrupt_num;
424 }
425 }
426
427 /*
428 * Having serviced the interrupt first, look at the interrupted stack depth.
429 */
430 if (!user_mode) {
431 uint64_t depth = cpu_data_ptr[cnum]->cpu_kernel_stack
432 + sizeof(struct x86_kernel_state)
433 + sizeof(struct i386_exception_link *)
434 - rsp;
435 if (depth > kernel_stack_depth_max) {
436 kernel_stack_depth_max = (vm_offset_t)depth;
437 KERNEL_DEBUG_CONSTANT(
438 MACHDBG_CODE(DBG_MACH_SCHED, MACH_STACK_DEPTH),
439 (long) depth, (long) VM_KERNEL_UNSLIDE(rip), 0, 0, 0);
440 }
441 }
442 }
443
444 static inline void
445 reset_dr7(void)
446 {
447 long dr7 = 0x400; /* magic dr7 reset value; 32 bit on i386, 64 bit on x86_64 */
448 __asm__ volatile("mov %0,%%dr7" : : "r" (dr7));
449 }
450 #if MACH_KDP
451 unsigned kdp_has_active_watchpoints = 0;
452 #define NO_WATCHPOINTS (!kdp_has_active_watchpoints)
453 #else
454 #define NO_WATCHPOINTS 1
455 #endif
456 /*
457 * Trap from kernel mode. Only page-fault errors are recoverable,
458 * and then only in special circumstances. All other errors are
459 * fatal. Return value indicates if trap was handled.
460 */
461
462 void
463 kernel_trap(
464 x86_saved_state_t *state,
465 uintptr_t *lo_spp)
466 {
467 #ifdef __i386__
468 x86_saved_state32_t *saved_state;
469 #else
470 x86_saved_state64_t *saved_state;
471 #endif
472 int code;
473 user_addr_t vaddr;
474 int type;
475 vm_map_t map = 0; /* protected by T_PAGE_FAULT */
476 kern_return_t result = KERN_FAILURE;
477 thread_t thread;
478 ast_t *myast;
479 boolean_t intr;
480 vm_prot_t prot;
481 struct recovery *rp;
482 vm_offset_t kern_ip;
483 #if NCOPY_WINDOWS > 0
484 int fault_in_copy_window = -1;
485 #endif
486 int is_user = 0;
487
488 thread = current_thread();
489
490 #ifdef __i386__
491 if (__improbable(is_saved_state64(state))) {
492 panic_64(state, 0, "Kernel trap with 64-bit state", FALSE);
493 }
494
495 saved_state = saved_state32(state);
496
497 /* Record cpu where state was captured (trampolines don't set this) */
498 saved_state->cpu = cpu_number();
499
500 vaddr = (user_addr_t)saved_state->cr2;
501 type = saved_state->trapno;
502 code = saved_state->err & 0xffff;
503 intr = (saved_state->efl & EFL_IF) != 0; /* state of ints at trap */
504 kern_ip = (vm_offset_t)saved_state->eip;
505 #else
506 if (__improbable(is_saved_state32(state)))
507 panic("kernel_trap(%p) with 32-bit state", state);
508 saved_state = saved_state64(state);
509
510 /* Record cpu where state was captured */
511 saved_state->isf.cpu = cpu_number();
512
513 vaddr = (user_addr_t)saved_state->cr2;
514 type = saved_state->isf.trapno;
515 code = (int)(saved_state->isf.err & 0xffff);
516 intr = (saved_state->isf.rflags & EFL_IF) != 0; /* state of ints at trap */
517 kern_ip = (vm_offset_t)saved_state->isf.rip;
518 #endif
519
520 myast = ast_pending();
521
522 perfASTCallback astfn = perfASTHook;
523 if (__improbable(astfn != NULL)) {
524 if (*myast & AST_CHUD_ALL)
525 astfn(AST_CHUD_ALL, myast);
526 } else
527 *myast &= ~AST_CHUD_ALL;
528
529 /*
530 * Is there a hook?
531 */
532 perfCallback fn = perfTrapHook;
533 if (__improbable(fn != NULL)) {
534 if (fn(type, NULL, 0, 0) == KERN_SUCCESS) {
535 /*
536 * If it succeeds, we are done...
537 */
538 return;
539 }
540 }
541
542 #if CONFIG_DTRACE
543 if (__improbable(tempDTraceTrapHook != NULL)) {
544 if (tempDTraceTrapHook(type, state, lo_spp, 0) == KERN_SUCCESS) {
545 /*
546 * If it succeeds, we are done...
547 */
548 return;
549 }
550 }
551 #endif /* CONFIG_DTRACE */
552
553 /*
554 * we come here with interrupts off as we don't want to recurse
555 * on preemption below. but we do want to re-enable interrupts
556 * as soon we possibly can to hold latency down
557 */
558 if (__improbable(T_PREEMPT == type)) {
559 ast_taken(AST_PREEMPTION, FALSE);
560
561 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
562 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
563 0, 0, 0, VM_KERNEL_UNSLIDE(kern_ip), 0);
564 return;
565 }
566
567 if (T_PAGE_FAULT == type) {
568 /*
569 * assume we're faulting in the kernel map
570 */
571 map = kernel_map;
572
573 if (__probable(thread != THREAD_NULL && thread->map != kernel_map)) {
574 #if NCOPY_WINDOWS > 0
575 vm_offset_t copy_window_base;
576 vm_offset_t kvaddr;
577 int window_index;
578
579 kvaddr = (vm_offset_t)vaddr;
580 /*
581 * must determine if fault occurred in
582 * the copy window while pre-emption is
583 * disabled for this processor so that
584 * we only need to look at the window
585 * associated with this processor
586 */
587 copy_window_base = current_cpu_datap()->cpu_copywindow_base;
588
589 if (kvaddr >= copy_window_base && kvaddr < (copy_window_base + (NBPDE * NCOPY_WINDOWS)) ) {
590
591 window_index = (int)((kvaddr - copy_window_base) / NBPDE);
592
593 if (thread->machine.copy_window[window_index].user_base != (user_addr_t)-1) {
594
595 kvaddr -= (copy_window_base + (NBPDE * window_index));
596 vaddr = thread->machine.copy_window[window_index].user_base + kvaddr;
597
598 map = thread->map;
599 fault_in_copy_window = window_index;
600 }
601 is_user = -1;
602 }
603 #else
604 if (__probable(vaddr < VM_MAX_USER_PAGE_ADDRESS)) {
605 /* fault occurred in userspace */
606 map = thread->map;
607 is_user = -1;
608
609 /* Intercept a potential Supervisor Mode Execute
610 * Protection fault. These criteria identify
611 * both NX faults and SMEP faults, but both
612 * are fatal. We avoid checking PTEs (racy).
613 * (The VM could just redrive a SMEP fault, hence
614 * the intercept).
615 */
616 if (__improbable((code == (T_PF_PROT | T_PF_EXECUTE)) && (pmap_smep_enabled) && (saved_state->isf.rip == vaddr))) {
617 goto debugger_entry;
618 }
619
620 /*
621 * If we're not sharing cr3 with the user
622 * and we faulted in copyio,
623 * then switch cr3 here and dismiss the fault.
624 */
625 if (no_shared_cr3 &&
626 (thread->machine.specFlags&CopyIOActive) &&
627 map->pmap->pm_cr3 != get_cr3_base()) {
628 pmap_assert(current_cpu_datap()->cpu_pmap_pcid_enabled == FALSE);
629 set_cr3_raw(map->pmap->pm_cr3);
630 return;
631 }
632 }
633 #endif
634 }
635 }
636 user_addr_t kd_vaddr = is_user ? vaddr : VM_KERNEL_UNSLIDE(vaddr);
637 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
638 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
639 (unsigned)(kd_vaddr >> 32), (unsigned)kd_vaddr, is_user,
640 VM_KERNEL_UNSLIDE(kern_ip), 0);
641
642
643 (void) ml_set_interrupts_enabled(intr);
644
645 switch (type) {
646
647 case T_NO_FPU:
648 fpnoextflt();
649 return;
650
651 case T_FPU_FAULT:
652 fpextovrflt();
653 return;
654
655 case T_FLOATING_POINT_ERROR:
656 fpexterrflt();
657 return;
658
659 case T_SSE_FLOAT_ERROR:
660 fpSSEexterrflt();
661 return;
662 case T_DEBUG:
663 #ifdef __i386__
664 if ((saved_state->efl & EFL_TF) == 0 && NO_WATCHPOINTS)
665 #else
666 if ((saved_state->isf.rflags & EFL_TF) == 0 && NO_WATCHPOINTS)
667 #endif
668 {
669 /* We've somehow encountered a debug
670 * register match that does not belong
671 * to the kernel debugger.
672 * This isn't supposed to happen.
673 */
674 reset_dr7();
675 return;
676 }
677 goto debugger_entry;
678 #ifdef __x86_64__
679 case T_INT3:
680 goto debugger_entry;
681 #endif
682 case T_PAGE_FAULT:
683
684 #if CONFIG_DTRACE
685 if (thread != THREAD_NULL && thread->options & TH_OPT_DTRACE) { /* Executing under dtrace_probe? */
686 if (dtrace_tally_fault(vaddr)) { /* Should a fault under dtrace be ignored? */
687 /*
688 * DTrace has "anticipated" the possibility of this fault, and has
689 * established the suitable recovery state. Drop down now into the
690 * recovery handling code in "case T_GENERAL_PROTECTION:".
691 */
692 goto FALL_THROUGH;
693 }
694 }
695 #endif /* CONFIG_DTRACE */
696
697 prot = VM_PROT_READ;
698
699 if (code & T_PF_WRITE)
700 prot |= VM_PROT_WRITE;
701 #if PAE
702 if (code & T_PF_EXECUTE)
703 prot |= VM_PROT_EXECUTE;
704 #endif
705
706 result = vm_fault(map,
707 vm_map_trunc_page(vaddr),
708 prot,
709 FALSE,
710 THREAD_UNINT, NULL, 0);
711
712 if (result == KERN_SUCCESS) {
713 #if NCOPY_WINDOWS > 0
714 if (fault_in_copy_window != -1) {
715 ml_set_interrupts_enabled(FALSE);
716 copy_window_fault(thread, map,
717 fault_in_copy_window);
718 (void) ml_set_interrupts_enabled(intr);
719 }
720 #endif /* NCOPY_WINDOWS > 0 */
721 return;
722 }
723 /*
724 * fall through
725 */
726 #if CONFIG_DTRACE
727 FALL_THROUGH:
728 #endif /* CONFIG_DTRACE */
729
730 case T_GENERAL_PROTECTION:
731 /*
732 * If there is a failure recovery address
733 * for this fault, go there.
734 */
735 for (rp = recover_table; rp < recover_table_end; rp++) {
736 if (kern_ip == rp->fault_addr) {
737 set_recovery_ip(saved_state, rp->recover_addr);
738 return;
739 }
740 }
741
742 /*
743 * Check thread recovery address also.
744 */
745 if (thread != THREAD_NULL && thread->recover) {
746 set_recovery_ip(saved_state, thread->recover);
747 thread->recover = 0;
748 return;
749 }
750 /*
751 * Unanticipated page-fault errors in kernel
752 * should not happen.
753 *
754 * fall through...
755 */
756 default:
757 /*
758 * Exception 15 is reserved but some chips may generate it
759 * spuriously. Seen at startup on AMD Athlon-64.
760 */
761 if (type == 15) {
762 kprintf("kernel_trap() ignoring spurious trap 15\n");
763 return;
764 }
765 debugger_entry:
766 /* Ensure that the i386_kernel_state at the base of the
767 * current thread's stack (if any) is synchronized with the
768 * context at the moment of the trap, to facilitate
769 * access through the debugger.
770 */
771 sync_iss_to_iks(state);
772 #if MACH_KDP
773 if (current_debugger != KDB_CUR_DB) {
774 if (kdp_i386_trap(type, saved_state, result, (vm_offset_t)vaddr))
775 return;
776 }
777 #endif
778 }
779 pal_cli();
780 panic_trap(saved_state);
781 /*
782 * NO RETURN
783 */
784 }
785
786
787 #ifdef __i386__
788 static void
789 set_recovery_ip(x86_saved_state32_t *saved_state, vm_offset_t ip)
790 {
791 saved_state->eip = ip;
792 }
793 #else
794 static void
795 set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip)
796 {
797 saved_state->isf.rip = ip;
798 }
799 #endif
800
801
802 #ifdef __i386__
803 static void
804 panic_trap(x86_saved_state32_t *regs)
805 {
806 const char *trapname = "Unknown";
807 pal_cr_t cr0, cr2, cr3, cr4;
808
809 pal_get_control_registers( &cr0, &cr2, &cr3, &cr4 );
810
811 /*
812 * Issue an I/O port read if one has been requested - this is an
813 * event logic analyzers can use as a trigger point.
814 */
815 panic_io_port_read();
816
817 kprintf("panic trap number 0x%x, eip 0x%x\n", regs->trapno, regs->eip);
818 kprintf("cr0 0x%08x cr2 0x%08x cr3 0x%08x cr4 0x%08x\n",
819 cr0, cr2, cr3, cr4);
820
821 if (regs->trapno < TRAP_TYPES)
822 trapname = trap_type[regs->trapno];
823 #undef panic
824 panic("Kernel trap at 0x%08x, type %d=%s, registers:\n"
825 "CR0: 0x%08x, CR2: 0x%08x, CR3: 0x%08x, CR4: 0x%08x\n"
826 "EAX: 0x%08x, EBX: 0x%08x, ECX: 0x%08x, EDX: 0x%08x\n"
827 "CR2: 0x%08x, EBP: 0x%08x, ESI: 0x%08x, EDI: 0x%08x\n"
828 "EFL: 0x%08x, EIP: 0x%08x, CS: 0x%08x, DS: 0x%08x\n"
829 "Error code: 0x%08x%s\n",
830 regs->eip, regs->trapno, trapname, cr0, cr2, cr3, cr4,
831 regs->eax,regs->ebx,regs->ecx,regs->edx,
832 regs->cr2,regs->ebp,regs->esi,regs->edi,
833 regs->efl,regs->eip,regs->cs & 0xFFFF, regs->ds & 0xFFFF, regs->err,
834 virtualized ? " VMM" : "");
835 /*
836 * This next statement is not executed,
837 * but it's needed to stop the compiler using tail call optimization
838 * for the panic call - which confuses the subsequent backtrace.
839 */
840 cr0 = 0;
841 }
842 #else
843
844
845 static void
846 panic_trap(x86_saved_state64_t *regs)
847 {
848 const char *trapname = "Unknown";
849 pal_cr_t cr0, cr2, cr3, cr4;
850 boolean_t potential_smep_fault = FALSE, potential_kernel_NX_fault = FALSE;
851
852 pal_get_control_registers( &cr0, &cr2, &cr3, &cr4 );
853 assert(ml_get_interrupts_enabled() == FALSE);
854 current_cpu_datap()->cpu_fatal_trap_state = regs;
855 /*
856 * Issue an I/O port read if one has been requested - this is an
857 * event logic analyzers can use as a trigger point.
858 */
859 panic_io_port_read();
860
861 kprintf("panic trap number 0x%x, rip 0x%016llx\n",
862 regs->isf.trapno, regs->isf.rip);
863 kprintf("cr0 0x%016llx cr2 0x%016llx cr3 0x%016llx cr4 0x%016llx\n",
864 cr0, cr2, cr3, cr4);
865
866 if (regs->isf.trapno < TRAP_TYPES)
867 trapname = trap_type[regs->isf.trapno];
868
869 if ((regs->isf.trapno == T_PAGE_FAULT) && (regs->isf.err == (T_PF_PROT | T_PF_EXECUTE)) && (regs->isf.rip == regs->cr2)) {
870 if (pmap_smep_enabled && (regs->isf.rip < VM_MAX_USER_PAGE_ADDRESS)) {
871 potential_smep_fault = TRUE;
872 } else if (regs->isf.rip >= VM_MIN_KERNEL_AND_KEXT_ADDRESS) {
873 potential_kernel_NX_fault = TRUE;
874 }
875 }
876
877 #undef panic
878 panic("Kernel trap at 0x%016llx, type %d=%s, registers:\n"
879 "CR0: 0x%016llx, CR2: 0x%016llx, CR3: 0x%016llx, CR4: 0x%016llx\n"
880 "RAX: 0x%016llx, RBX: 0x%016llx, RCX: 0x%016llx, RDX: 0x%016llx\n"
881 "RSP: 0x%016llx, RBP: 0x%016llx, RSI: 0x%016llx, RDI: 0x%016llx\n"
882 "R8: 0x%016llx, R9: 0x%016llx, R10: 0x%016llx, R11: 0x%016llx\n"
883 "R12: 0x%016llx, R13: 0x%016llx, R14: 0x%016llx, R15: 0x%016llx\n"
884 "RFL: 0x%016llx, RIP: 0x%016llx, CS: 0x%016llx, SS: 0x%016llx\n"
885 "Fault CR2: 0x%016llx, Error code: 0x%016llx, Fault CPU: 0x%x%s%s%s\n",
886 regs->isf.rip, regs->isf.trapno, trapname,
887 cr0, cr2, cr3, cr4,
888 regs->rax, regs->rbx, regs->rcx, regs->rdx,
889 regs->isf.rsp, regs->rbp, regs->rsi, regs->rdi,
890 regs->r8, regs->r9, regs->r10, regs->r11,
891 regs->r12, regs->r13, regs->r14, regs->r15,
892 regs->isf.rflags, regs->isf.rip, regs->isf.cs & 0xFFFF,
893 regs->isf.ss & 0xFFFF,regs->cr2, regs->isf.err, regs->isf.cpu,
894 virtualized ? " VMM" : "",
895 potential_kernel_NX_fault ? " Kernel NX fault" : "",
896 potential_smep_fault ? " SMEP/User NX fault" : "");
897 /*
898 * This next statement is not executed,
899 * but it's needed to stop the compiler using tail call optimization
900 * for the panic call - which confuses the subsequent backtrace.
901 */
902 cr0 = 0;
903 }
904 #endif
905
906 #if CONFIG_DTRACE
907 extern kern_return_t dtrace_user_probe(x86_saved_state_t *);
908 #endif
909
910 /*
911 * Trap from user mode.
912 */
913 void
914 user_trap(
915 x86_saved_state_t *saved_state)
916 {
917 int exc;
918 int err;
919 mach_exception_code_t code;
920 mach_exception_subcode_t subcode;
921 int type;
922 user_addr_t vaddr;
923 vm_prot_t prot;
924 thread_t thread = current_thread();
925 ast_t *myast;
926 kern_return_t kret;
927 user_addr_t rip;
928 unsigned long dr6 = 0; /* 32 bit for i386, 64 bit for x86_64 */
929
930 assert((is_saved_state32(saved_state) && !thread_is_64bit(thread)) ||
931 (is_saved_state64(saved_state) && thread_is_64bit(thread)));
932
933 if (is_saved_state64(saved_state)) {
934 x86_saved_state64_t *regs;
935
936 regs = saved_state64(saved_state);
937
938 /* Record cpu where state was captured */
939 regs->isf.cpu = cpu_number();
940
941 type = regs->isf.trapno;
942 err = (int)regs->isf.err & 0xffff;
943 vaddr = (user_addr_t)regs->cr2;
944 rip = (user_addr_t)regs->isf.rip;
945 } else {
946 x86_saved_state32_t *regs;
947
948 regs = saved_state32(saved_state);
949
950 /* Record cpu where state was captured */
951 regs->cpu = cpu_number();
952
953 type = regs->trapno;
954 err = regs->err & 0xffff;
955 vaddr = (user_addr_t)regs->cr2;
956 rip = (user_addr_t)regs->eip;
957 }
958
959 if ((type == T_DEBUG) && thread->machine.ids) {
960 unsigned long clear = 0;
961 /* Stash and clear this processor's DR6 value, in the event
962 * this was a debug register match
963 */
964 __asm__ volatile ("mov %%db6, %0" : "=r" (dr6));
965 __asm__ volatile ("mov %0, %%db6" : : "r" (clear));
966 }
967
968 pal_sti();
969
970 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
971 (MACHDBG_CODE(DBG_MACH_EXCP_UTRAP_x86, type)) | DBG_FUNC_NONE,
972 (unsigned)(vaddr>>32), (unsigned)vaddr,
973 (unsigned)(rip>>32), (unsigned)rip, 0);
974
975 code = 0;
976 subcode = 0;
977 exc = 0;
978
979 #if DEBUG_TRACE
980 kprintf("user_trap(0x%08x) type=%d vaddr=0x%016llx\n",
981 saved_state, type, vaddr);
982 #endif
983
984 perfASTCallback astfn = perfASTHook;
985 if (__improbable(astfn != NULL)) {
986 myast = ast_pending();
987 if (*myast & AST_CHUD_ALL) {
988 astfn(AST_CHUD_ALL, myast);
989 }
990 }
991
992 /* Is there a hook? */
993 perfCallback fn = perfTrapHook;
994 if (__improbable(fn != NULL)) {
995 if (fn(type, saved_state, 0, 0) == KERN_SUCCESS)
996 return; /* If it succeeds, we are done... */
997 }
998
999 /*
1000 * DTrace does not consume all user traps, only INT_3's for now.
1001 * Avoid needlessly calling tempDTraceTrapHook here, and let the
1002 * INT_3 case handle them.
1003 */
1004 DEBUG_KPRINT_SYSCALL_MASK(1,
1005 "user_trap: type=0x%x(%s) err=0x%x cr2=%p rip=%p\n",
1006 type, trap_type[type], err, (void *)(long) vaddr, (void *)(long) rip);
1007
1008 switch (type) {
1009
1010 case T_DIVIDE_ERROR:
1011 exc = EXC_ARITHMETIC;
1012 code = EXC_I386_DIV;
1013 break;
1014
1015 case T_DEBUG:
1016 {
1017 pcb_t pcb;
1018 /*
1019 * Update the PCB with this processor's DR6 value
1020 * in the event this was a debug register match.
1021 */
1022 pcb = THREAD_TO_PCB(thread);
1023 if (pcb->ids) {
1024 /*
1025 * We can get and set the status register
1026 * in 32-bit mode even on a 64-bit thread
1027 * because the high order bits are not
1028 * used on x86_64
1029 */
1030 if (thread_is_64bit(thread)) {
1031 x86_debug_state64_t *ids = pcb->ids;
1032 ids->dr6 = dr6;
1033 } else { /* 32 bit thread */
1034 x86_debug_state32_t *ids = pcb->ids;
1035 ids->dr6 = (uint32_t) dr6;
1036 }
1037 }
1038 exc = EXC_BREAKPOINT;
1039 code = EXC_I386_SGL;
1040 break;
1041 }
1042 case T_INT3:
1043 #if CONFIG_DTRACE
1044 if (dtrace_user_probe(saved_state) == KERN_SUCCESS)
1045 return; /* If it succeeds, we are done... */
1046 #endif
1047 exc = EXC_BREAKPOINT;
1048 code = EXC_I386_BPT;
1049 break;
1050
1051 case T_OVERFLOW:
1052 exc = EXC_ARITHMETIC;
1053 code = EXC_I386_INTO;
1054 break;
1055
1056 case T_OUT_OF_BOUNDS:
1057 exc = EXC_SOFTWARE;
1058 code = EXC_I386_BOUND;
1059 break;
1060
1061 case T_INVALID_OPCODE:
1062 exc = EXC_BAD_INSTRUCTION;
1063 code = EXC_I386_INVOP;
1064 break;
1065
1066 case T_NO_FPU:
1067 fpnoextflt();
1068 return;
1069
1070 case T_FPU_FAULT:
1071 fpextovrflt(); /* Propagates exception directly, doesn't return */
1072 return;
1073
1074 case T_INVALID_TSS: /* invalid TSS == iret with NT flag set */
1075 exc = EXC_BAD_INSTRUCTION;
1076 code = EXC_I386_INVTSSFLT;
1077 subcode = err;
1078 break;
1079
1080 case T_SEGMENT_NOT_PRESENT:
1081 exc = EXC_BAD_INSTRUCTION;
1082 code = EXC_I386_SEGNPFLT;
1083 subcode = err;
1084 break;
1085
1086 case T_STACK_FAULT:
1087 exc = EXC_BAD_INSTRUCTION;
1088 code = EXC_I386_STKFLT;
1089 subcode = err;
1090 break;
1091
1092 case T_GENERAL_PROTECTION:
1093 /*
1094 * There's a wide range of circumstances which generate this
1095 * class of exception. From user-space, many involve bad
1096 * addresses (such as a non-canonical 64-bit address).
1097 * So we map this to EXC_BAD_ACCESS (and thereby SIGSEGV).
1098 * The trouble is cr2 doesn't contain the faulting address;
1099 * we'd need to decode the faulting instruction to really
1100 * determine this. We'll leave that to debuggers.
1101 * However, attempted execution of privileged instructions
1102 * (e.g. cli) also generate GP faults and so we map these to
1103 * to EXC_BAD_ACCESS (and thence SIGSEGV) also - rather than
1104 * EXC_BAD_INSTRUCTION which is more accurate. We just can't
1105 * win!
1106 */
1107 exc = EXC_BAD_ACCESS;
1108 code = EXC_I386_GPFLT;
1109 subcode = err;
1110 break;
1111
1112 case T_PAGE_FAULT:
1113 prot = VM_PROT_READ;
1114
1115 if (err & T_PF_WRITE)
1116 prot |= VM_PROT_WRITE;
1117 #if PAE
1118 if (__improbable(err & T_PF_EXECUTE))
1119 prot |= VM_PROT_EXECUTE;
1120 #endif
1121 kret = vm_fault(thread->map, vm_map_trunc_page(vaddr),
1122 prot, FALSE,
1123 THREAD_ABORTSAFE, NULL, 0);
1124
1125 user_page_fault_continue(kret);
1126
1127 /* NOTREACHED */
1128 break;
1129
1130 case T_SSE_FLOAT_ERROR:
1131 fpSSEexterrflt(); /* Propagates exception directly, doesn't return */
1132 return;
1133
1134
1135 case T_FLOATING_POINT_ERROR:
1136 fpexterrflt(); /* Propagates exception directly, doesn't return */
1137 return;
1138
1139 case T_DTRACE_RET:
1140 #if CONFIG_DTRACE
1141 if (dtrace_user_probe(saved_state) == KERN_SUCCESS)
1142 return; /* If it succeeds, we are done... */
1143 #endif
1144 /*
1145 * If we get an INT 0x7f when we do not expect to,
1146 * treat it as an illegal instruction
1147 */
1148 exc = EXC_BAD_INSTRUCTION;
1149 code = EXC_I386_INVOP;
1150 break;
1151
1152 default:
1153 panic("Unexpected user trap, type %d", type);
1154 return;
1155 }
1156 /* Note: Codepaths that directly return from user_trap() have pending
1157 * ASTs processed in locore
1158 */
1159 i386_exception(exc, code, subcode);
1160 /* NOTREACHED */
1161 }
1162
1163
1164 /*
1165 * Handle AST traps for i386.
1166 */
1167
1168 extern void log_thread_action (thread_t, char *);
1169
1170 void
1171 i386_astintr(int preemption)
1172 {
1173 ast_t mask = AST_ALL;
1174 spl_t s;
1175
1176 if (preemption)
1177 mask = AST_PREEMPTION;
1178
1179 s = splsched();
1180
1181 ast_taken(mask, s);
1182
1183 splx(s);
1184 }
1185
1186 /*
1187 * Handle exceptions for i386.
1188 *
1189 * If we are an AT bus machine, we must turn off the AST for a
1190 * delayed floating-point exception.
1191 *
1192 * If we are providing floating-point emulation, we may have
1193 * to retrieve the real register values from the floating point
1194 * emulator.
1195 */
1196 void
1197 i386_exception(
1198 int exc,
1199 mach_exception_code_t code,
1200 mach_exception_subcode_t subcode)
1201 {
1202 mach_exception_data_type_t codes[EXCEPTION_CODE_MAX];
1203
1204 DEBUG_KPRINT_SYSCALL_MACH("i386_exception: exc=%d code=0x%llx subcode=0x%llx\n",
1205 exc, code, subcode);
1206 codes[0] = code; /* new exception interface */
1207 codes[1] = subcode;
1208 exception_triage(exc, codes, 2);
1209 /*NOTREACHED*/
1210 }
1211
1212
1213 /* Synchronize a thread's i386_kernel_state (if any) with the given
1214 * i386_saved_state_t obtained from the trap/IPI handler; called in
1215 * kernel_trap() prior to entering the debugger, and when receiving
1216 * an "MP_KDP" IPI.
1217 */
1218
1219 void
1220 sync_iss_to_iks(x86_saved_state_t *saved_state)
1221 {
1222 struct x86_kernel_state *iks;
1223 vm_offset_t kstack;
1224 boolean_t record_active_regs = FALSE;
1225
1226 /* The PAL may have a special way to sync registers */
1227 if( saved_state->flavor == THREAD_STATE_NONE )
1228 pal_get_kern_regs( saved_state );
1229
1230 if ((kstack = current_thread()->kernel_stack) != 0) {
1231 #ifdef __i386__
1232 x86_saved_state32_t *regs = saved_state32(saved_state);
1233 #else
1234 x86_saved_state64_t *regs = saved_state64(saved_state);
1235 #endif
1236
1237 iks = STACK_IKS(kstack);
1238
1239 /* Did we take the trap/interrupt in kernel mode? */
1240 #ifdef __i386__
1241 if (regs == USER_REGS32(current_thread()))
1242 record_active_regs = TRUE;
1243 else {
1244 iks->k_ebx = regs->ebx;
1245 iks->k_esp = (int)regs;
1246 iks->k_ebp = regs->ebp;
1247 iks->k_edi = regs->edi;
1248 iks->k_esi = regs->esi;
1249 iks->k_eip = regs->eip;
1250 }
1251 #else
1252 if (regs == USER_REGS64(current_thread()))
1253 record_active_regs = TRUE;
1254 else {
1255 iks->k_rbx = regs->rbx;
1256 iks->k_rsp = regs->isf.rsp;
1257 iks->k_rbp = regs->rbp;
1258 iks->k_r12 = regs->r12;
1259 iks->k_r13 = regs->r13;
1260 iks->k_r14 = regs->r14;
1261 iks->k_r15 = regs->r15;
1262 iks->k_rip = regs->isf.rip;
1263 }
1264 #endif
1265 }
1266
1267 if (record_active_regs == TRUE) {
1268 #ifdef __i386__
1269 /* Show the trap handler path */
1270 __asm__ volatile("movl %%ebx, %0" : "=m" (iks->k_ebx));
1271 __asm__ volatile("movl %%esp, %0" : "=m" (iks->k_esp));
1272 __asm__ volatile("movl %%ebp, %0" : "=m" (iks->k_ebp));
1273 __asm__ volatile("movl %%edi, %0" : "=m" (iks->k_edi));
1274 __asm__ volatile("movl %%esi, %0" : "=m" (iks->k_esi));
1275 /* "Current" instruction pointer */
1276 __asm__ volatile("movl $1f, %0\n1:" : "=m" (iks->k_eip));
1277 #else
1278 /* Show the trap handler path */
1279 __asm__ volatile("movq %%rbx, %0" : "=m" (iks->k_rbx));
1280 __asm__ volatile("movq %%rsp, %0" : "=m" (iks->k_rsp));
1281 __asm__ volatile("movq %%rbp, %0" : "=m" (iks->k_rbp));
1282 __asm__ volatile("movq %%r12, %0" : "=m" (iks->k_r12));
1283 __asm__ volatile("movq %%r13, %0" : "=m" (iks->k_r13));
1284 __asm__ volatile("movq %%r14, %0" : "=m" (iks->k_r14));
1285 __asm__ volatile("movq %%r15, %0" : "=m" (iks->k_r15));
1286 /* "Current" instruction pointer */
1287 __asm__ volatile("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:"
1288 : "=m" (iks->k_rip)
1289 :
1290 : "rax");
1291 #endif
1292 }
1293 }
1294
1295 /*
1296 * This is used by the NMI interrupt handler (from mp.c) to
1297 * uncondtionally sync the trap handler context to the IKS
1298 * irrespective of whether the NMI was fielded in kernel
1299 * or user space.
1300 */
1301 void
1302 sync_iss_to_iks_unconditionally(__unused x86_saved_state_t *saved_state) {
1303 struct x86_kernel_state *iks;
1304 vm_offset_t kstack;
1305
1306 if ((kstack = current_thread()->kernel_stack) != 0) {
1307 iks = STACK_IKS(kstack);
1308 #ifdef __i386__
1309 /* Display the trap handler path */
1310 __asm__ volatile("movl %%ebx, %0" : "=m" (iks->k_ebx));
1311 __asm__ volatile("movl %%esp, %0" : "=m" (iks->k_esp));
1312 __asm__ volatile("movl %%ebp, %0" : "=m" (iks->k_ebp));
1313 __asm__ volatile("movl %%edi, %0" : "=m" (iks->k_edi));
1314 __asm__ volatile("movl %%esi, %0" : "=m" (iks->k_esi));
1315 /* "Current" instruction pointer */
1316 __asm__ volatile("movl $1f, %0\n1:" : "=m" (iks->k_eip));
1317 #else
1318 /* Display the trap handler path */
1319 __asm__ volatile("movq %%rbx, %0" : "=m" (iks->k_rbx));
1320 __asm__ volatile("movq %%rsp, %0" : "=m" (iks->k_rsp));
1321 __asm__ volatile("movq %%rbp, %0" : "=m" (iks->k_rbp));
1322 __asm__ volatile("movq %%r12, %0" : "=m" (iks->k_r12));
1323 __asm__ volatile("movq %%r13, %0" : "=m" (iks->k_r13));
1324 __asm__ volatile("movq %%r14, %0" : "=m" (iks->k_r14));
1325 __asm__ volatile("movq %%r15, %0" : "=m" (iks->k_r15));
1326 /* "Current" instruction pointer */
1327 __asm__ volatile("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:" : "=m" (iks->k_rip)::"rax");
1328 #endif
1329 }
1330 }
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