osfmk/x86_64/boot_pt.c

   1 /*
   2  * Copyright (c) 2011 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 #include <i386/pmap.h>
  29
  30 /*
  31  * These pagetables are used during early processor startup during
  32  * the transition from protected mode to 64-bit mode and the jump
  33  * to high kernel address space.
  34  *
  35  * They are required to be at the base of the kernel and specifically
  36  * the base of the special __HIB section.
  37  *
  38  * These tables are statically-defined as physical-zero-based.
  39  * Startup code in start.s rebases these according to the actual physical
  40  * base address.
  41  */
  42
  43 /*
  44  * NB: This must be located at the kernel's base address!
  45  */
  46 #define PML4_PROT (INTEL_PTE_VALID | INTEL_PTE_WRITE)
  47 pml4_entry_t    BootPML4[PTE_PER_PAGE]
  48 __attribute__((section("__HIB, __bootPT"))) = {
  49         [0]                     = ((uint64_t)(PAGE_SIZE) | PML4_PROT),
  50         [KERNEL_PML4_INDEX]     = ((uint64_t)(PAGE_SIZE) | PML4_PROT),
  51 };
  52
  53 #define PDPT_PROT (INTEL_PTE_VALID | INTEL_PTE_WRITE)
  54 pdpt_entry_t    BootPDPT[PTE_PER_PAGE]
  55 __attribute__((section("__HIB, __bootPT"))) = {
  56         [0]     = ((uint64_t)(2 * PAGE_SIZE) | PDPT_PROT),
  57         [1]     = ((uint64_t)(3 * PAGE_SIZE) | PDPT_PROT),
  58         [2]     = ((uint64_t)(4 * PAGE_SIZE) | PDPT_PROT),
  59         [3]     = ((uint64_t)(5 * PAGE_SIZE) | PDPT_PROT),
  60 };
  61
  62 #if NPGPTD != 4
  63 #error Please update boot_pt.c to reflect the new value of NPGPTD
  64 #endif
  65
  66 #if MACHINE_BOOTSTRAPPTD
  67
  68 #define PDT_PROT (INTEL_PTE_PS | INTEL_PTE_VALID | INTEL_PTE_WRITE)
  69 #define ID_MAP_2MEG(x)  [(x)] = ((((uint64_t)(x)) << 21) | (PDT_PROT)),
  70
  71 #define L0(x, n)  x(n)
  72 #define L1(x, n)  L0(x,n-1)     L0(x,n)
  73 #define L2(x, n)  L1(x,n-2)     L1(x,n)
  74 #define L3(x, n)  L2(x,n-4)     L2(x,n)
  75 #define L4(x, n)  L3(x,n-8)     L3(x,n)
  76 #define L5(x, n)  L4(x,n-16)    L4(x,n)
  77 #define L6(x, n)  L5(x,n-32)    L5(x,n)
  78 #define L7(x, n)  L6(x,n-64)    L6(x,n)
  79 #define L8(x, n)  L7(x,n-128)   L7(x,n)
  80 #define L9(x, n)  L8(x,n-256)   L8(x,n)
  81 #define L10(x, n) L9(x,n-512)   L9(x,n)
  82 #define L11(x, n) L10(x,n-1024) L10(x,n)
  83
  84 #define FOR_0_TO_2047(x) L11(x,2047)
  85
  86 pd_entry_t      BootPTD[2048]
  87 __attribute__((section("__HIB, __bootPT"))) = {
  88         FOR_0_TO_2047(ID_MAP_2MEG)
  89 };
  90 #endif /* MACHINE_BOOTSTRAPPTD */