[apple/xnu.git] / osfmk / i386 / machine_check.c

/*
 * Copyright (c) 2007-2011 Apple Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */

#include <kern/kalloc.h>
#include <mach/mach_time.h>
#include <i386/cpu_data.h>
#include <i386/cpuid.h>
#include <i386/cpu_topology.h>
#include <i386/cpu_threads.h>
#include <i386/lapic.h>
#include <i386/machine_cpu.h>
#include <i386/machine_check.h>
#include <i386/proc_reg.h>

/*
 * At the time of the machine-check exception, all hardware-threads panic.
 * Each thread saves the state of its MCA registers to its per-cpu data area.
 *
 * State reporting is serialized so one thread dumps all valid state for all
 * threads to the panic log. This may entail spinning waiting for other
 * threads to complete saving state to memory. A timeout applies to this wait
 * -- in particular, a 3-strikes timeout may prevent a thread from taking
 * part is the affair.
 */

#define IF(bool,str)	((bool) ? (str) : "")

static boolean_t	mca_initialized = FALSE;
static boolean_t	mca_MCE_present = FALSE;
static boolean_t	mca_MCA_present = FALSE;
static uint32_t		mca_family = 0;
static unsigned int	mca_error_bank_count = 0;
static boolean_t	mca_control_MSR_present = FALSE;
static boolean_t	mca_cmci_present = FALSE;
static ia32_mcg_cap_t	ia32_mcg_cap;
decl_simple_lock_data(static, mca_lock);

typedef struct {
	ia32_mci_ctl_t		mca_mci_ctl;
	ia32_mci_status_t	mca_mci_status;
	ia32_mci_misc_t		mca_mci_misc;
	ia32_mci_addr_t		mca_mci_addr;
} mca_mci_bank_t;

typedef struct mca_state {
	boolean_t		mca_is_saved;
	boolean_t		mca_is_valid;	/* some state is valid */
	ia32_mcg_ctl_t		mca_mcg_ctl;
	ia32_mcg_status_t	mca_mcg_status;
	mca_mci_bank_t		mca_error_bank[0];
} mca_state_t;

typedef enum {
	CLEAR,
	DUMPING,
	DUMPED
} mca_dump_state_t;
static volatile mca_dump_state_t mca_dump_state = CLEAR;

static void
mca_get_availability(void)
{
	uint64_t	features = cpuid_info()->cpuid_features;
	uint32_t	family =   cpuid_info()->cpuid_family;
	uint32_t	model =    cpuid_info()->cpuid_model;
	uint32_t	stepping = cpuid_info()->cpuid_stepping;

	if ((model == CPUID_MODEL_HASWELL     && stepping < 3) ||
	    (model == CPUID_MODEL_HASWELL_ULT && stepping < 1) ||
	    (model == CPUID_MODEL_CRYSTALWELL && stepping < 1))
		panic("Haswell pre-C0 steppings are not supported");

	mca_MCE_present = (features & CPUID_FEATURE_MCE) != 0;
	mca_MCA_present = (features & CPUID_FEATURE_MCA) != 0;
	mca_family = family;

	/*
	 * If MCA, the number of banks etc is reported by the IA32_MCG_CAP MSR.
	 */
	if (mca_MCA_present) {
		ia32_mcg_cap.u64 = rdmsr64(IA32_MCG_CAP);
		mca_error_bank_count = ia32_mcg_cap.bits.count;
		mca_control_MSR_present = ia32_mcg_cap.bits.mcg_ctl_p;
		mca_cmci_present = ia32_mcg_cap.bits.mcg_ext_corr_err_p;
	}
}

void
mca_cpu_init(void)
{
	unsigned int	i;

	/*
	 * The first (boot) processor is responsible for discovering the
	 * machine check architecture present on this machine.
	 */
	if (!mca_initialized) {
		mca_get_availability();
		mca_initialized = TRUE;
		simple_lock_init(&mca_lock, 0);
	}

	if (mca_MCA_present) {

		/* Enable all MCA features */
		if (mca_control_MSR_present)
			wrmsr64(IA32_MCG_CTL, IA32_MCG_CTL_ENABLE);
	
		switch (mca_family) {
		case 0x06:
			/* Enable all but mc0 */
			for (i = 1; i < mca_error_bank_count; i++)
				wrmsr64(IA32_MCi_CTL(i),0xFFFFFFFFFFFFFFFFULL); 
			
			/* Clear all errors */
			for (i = 0; i < mca_error_bank_count; i++)
				wrmsr64(IA32_MCi_STATUS(i), 0ULL);
			break;
		case 0x0F:
			/* Enable all banks */
			for (i = 0; i < mca_error_bank_count; i++)
				wrmsr64(IA32_MCi_CTL(i),0xFFFFFFFFFFFFFFFFULL); 
			
			/* Clear all errors */
			for (i = 0; i < mca_error_bank_count; i++)
				wrmsr64(IA32_MCi_STATUS(i), 0ULL);
			break;
		}
	}

	/* Enable machine check exception handling if available */
	if (mca_MCE_present) {
		set_cr4(get_cr4()|CR4_MCE);
	}
}

boolean_t
mca_is_cmci_present(void)
{
	if (!mca_initialized)
		mca_cpu_init();
	return mca_cmci_present;
}

void
mca_cpu_alloc(cpu_data_t	*cdp)
{
	vm_size_t	mca_state_size;

	/*
	 * Allocate space for an array of error banks.
	 */
	mca_state_size = sizeof(mca_state_t) +
				sizeof(mca_mci_bank_t) * mca_error_bank_count;
	cdp->cpu_mca_state = kalloc(mca_state_size);
	if (cdp->cpu_mca_state == NULL) {
		printf("mca_cpu_alloc() failed for cpu %d\n", cdp->cpu_number);
		return;
	}
	bzero((void *) cdp->cpu_mca_state, mca_state_size);

	/*
	 * If the boot processor is yet have its allocation made,
	 * do this now.
	 */
	if (cpu_datap(master_cpu)->cpu_mca_state == NULL)
		mca_cpu_alloc(cpu_datap(master_cpu));
}

static void
mca_save_state(mca_state_t *mca_state)
{
	mca_mci_bank_t  *bank;
	unsigned int	i;

	assert(!ml_get_interrupts_enabled() || get_preemption_level() > 0);

	if  (mca_state == NULL)
		return;

	mca_state->mca_mcg_ctl = mca_control_MSR_present ?
					rdmsr64(IA32_MCG_CTL) : 0ULL;	
	mca_state->mca_mcg_status.u64 = rdmsr64(IA32_MCG_STATUS);

 	bank = (mca_mci_bank_t *) &mca_state->mca_error_bank[0];
	for (i = 0; i < mca_error_bank_count; i++, bank++) {
		bank->mca_mci_ctl        = rdmsr64(IA32_MCi_CTL(i));	
		bank->mca_mci_status.u64 = rdmsr64(IA32_MCi_STATUS(i));	
		if (!bank->mca_mci_status.bits.val)
			continue;
		bank->mca_mci_misc = (bank->mca_mci_status.bits.miscv)?
					rdmsr64(IA32_MCi_MISC(i)) : 0ULL;	
		bank->mca_mci_addr = (bank->mca_mci_status.bits.addrv)?
					rdmsr64(IA32_MCi_ADDR(i)) : 0ULL;	
		mca_state->mca_is_valid = TRUE;
	} 

	/*
	 * If we're the first thread with MCA state, point our package to it
	 * and don't care about races
	 */
	if (x86_package()->mca_state == NULL)
		x86_package()->mca_state = mca_state;

	mca_state->mca_is_saved = TRUE;
}

void
mca_check_save(void)
{
	if (mca_dump_state > CLEAR)
		mca_save_state(current_cpu_datap()->cpu_mca_state);
}

static void
mca_report_cpu_info(void)
{
	i386_cpu_info_t *infop = cpuid_info();

	paniclog_append_noflush(" family: %d model: %d stepping: %d microcode: %d\n",
		infop->cpuid_family,
		infop->cpuid_model,
		infop->cpuid_stepping,
		infop->cpuid_microcode_version);
	paniclog_append_noflush(" signature: 0x%x\n",
		infop->cpuid_signature);
	paniclog_append_noflush(" %s\n",
		infop->cpuid_brand_string);

}

static void
mca_dump_bank(mca_state_t *state, int i)
{
	mca_mci_bank_t		*bank;
	ia32_mci_status_t	status;

	bank = &state->mca_error_bank[i];
	status = bank->mca_mci_status;
	if (!status.bits.val)
		return;

	paniclog_append_noflush(" IA32_MC%d_STATUS(0x%x): 0x%016qx\n",
		i, IA32_MCi_STATUS(i), status.u64);

	if (status.bits.addrv)
		paniclog_append_noflush(" IA32_MC%d_ADDR(0x%x):   0x%016qx\n",
			i, IA32_MCi_ADDR(i), bank->mca_mci_addr);

	if (status.bits.miscv)
		paniclog_append_noflush(" IA32_MC%d_MISC(0x%x):   0x%016qx\n",
			i, IA32_MCi_MISC(i), bank->mca_mci_misc);
}

static void
mca_cpu_dump_error_banks(mca_state_t *state)
{
	unsigned int 		i;

	if (!state->mca_is_valid)
		return;

	for (i = 0; i < mca_error_bank_count; i++ ) {
		mca_dump_bank(state, i);
	}
}

void
mca_dump(void)
{
	mca_state_t	*mca_state = current_cpu_datap()->cpu_mca_state;
	uint64_t	deadline;
	unsigned int	i = 0;

	/*
	 * Capture local MCA registers to per-cpu data.
	 */
	mca_save_state(mca_state);

	/*
	 * Serialize: the first caller controls dumping MCA registers,
	 * other threads spin meantime.
	 */
	simple_lock(&mca_lock);
	if (mca_dump_state > CLEAR) {
		simple_unlock(&mca_lock);
		while (mca_dump_state == DUMPING)
			cpu_pause();
		return;
	}
	mca_dump_state = DUMPING;
	simple_unlock(&mca_lock);

	/*
	 * Wait for all other hardware threads to save their state.
	 * Or timeout.
	 */
	deadline = mach_absolute_time() + LockTimeOut;
	while (mach_absolute_time() < deadline && i < real_ncpus) {
		if (!cpu_datap(i)->cpu_mca_state->mca_is_saved) {
			cpu_pause();
			continue;
		}
		i += 1;
	}

	/*
	 * Report machine-check capabilities:
	 */
	paniclog_append_noflush("Machine-check capabilities: 0x%016qx\n", ia32_mcg_cap.u64);

	mca_report_cpu_info();

	paniclog_append_noflush(" %d error-reporting banks\n", mca_error_bank_count);
 
	/*
	 * Dump all processor state:
	 */
	for (i = 0; i < real_ncpus; i++) {
		mca_state_t		*mcsp = cpu_datap(i)->cpu_mca_state;
		ia32_mcg_status_t	status;

		if (mcsp == NULL ||
		    mcsp->mca_is_saved == FALSE ||
		    mcsp->mca_mcg_status.u64 == 0 ||
		    !mcsp->mca_is_valid) {
			continue;
		}
		status = mcsp->mca_mcg_status;
		paniclog_append_noflush("Processor %d: IA32_MCG_STATUS: 0x%016qx\n",
			i, status.u64);
		mca_cpu_dump_error_banks(mcsp);
	}

	/* Update state to release any other threads. */
	mca_dump_state = DUMPED;
}


#if DEVELOPMENT || DEBUG
extern void mca_exception_panic(void);
extern void lapic_trigger_MC(void);
void mca_exception_panic(void)
{
	lapic_trigger_MC();
}
#endif
Commit	Line	Data
0c530ab8	1	/*
316670eb	2	* Copyright (c) 2007-2011 Apple Inc. All rights reserved.
0c530ab8 A	3	*
	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
	5	*
	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
	14	*
	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
	25	*
	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
	27	*/
	28
2d21ac55	29	#include <kern/kalloc.h>
593a1d5f	30	#include <mach/mach_time.h>
0c530ab8 A	31	#include <i386/cpu_data.h>
0c530ab8 A	32	#include <i386/cpuid.h>
593a1d5f A	33	#include <i386/cpu_topology.h>
593a1d5f A	34	#include <i386/cpu_threads.h>
15129b1c	35	#include <i386/lapic.h>
593a1d5f	36	#include <i386/machine_cpu.h>
0c530ab8 A	37	#include <i386/machine_check.h>
	38	#include <i386/proc_reg.h>
	39
316670eb A	40	/*
	41	* At the time of the machine-check exception, all hardware-threads panic.
	42	* Each thread saves the state of its MCA registers to its per-cpu data area.
	43	*
	44	* State reporting is serialized so one thread dumps all valid state for all
	45	* threads to the panic log. This may entail spinning waiting for other
	46	* threads to complete saving state to memory. A timeout applies to this wait
	47	* -- in particular, a 3-strikes timeout may prevent a thread from taking
	48	* part is the affair.
	49	*/
	50
0c530ab8 A	51	#define IF(bool,str) ((bool) ? (str) : "")
	52
	53	static boolean_t mca_initialized = FALSE;
	54	static boolean_t mca_MCE_present = FALSE;
	55	static boolean_t mca_MCA_present = FALSE;
2d21ac55	56	static uint32_t mca_family = 0;
0c530ab8 A	57	static unsigned int mca_error_bank_count = 0;
0c530ab8 A	58	static boolean_t mca_control_MSR_present = FALSE;
c910b4d9	59	static boolean_t mca_cmci_present = FALSE;
0c530ab8	60	static ia32_mcg_cap_t ia32_mcg_cap;
2d21ac55 A	61	decl_simple_lock_data(static, mca_lock);
	62
	63	typedef struct {
	64	ia32_mci_ctl_t mca_mci_ctl;
	65	ia32_mci_status_t mca_mci_status;
	66	ia32_mci_misc_t mca_mci_misc;
	67	ia32_mci_addr_t mca_mci_addr;
	68	} mca_mci_bank_t;
	69
	70	typedef struct mca_state {
316670eb A	71	boolean_t mca_is_saved;
316670eb A	72	boolean_t mca_is_valid; /* some state is valid */
2d21ac55 A	73	ia32_mcg_ctl_t mca_mcg_ctl;
	74	ia32_mcg_status_t mca_mcg_status;
	75	mca_mci_bank_t mca_error_bank[0];
	76	} mca_state_t;
0c530ab8	77
593a1d5f A	78	typedef enum {
	79	CLEAR,
	80	DUMPING,
	81	DUMPED
	82	} mca_dump_state_t;
	83	static volatile mca_dump_state_t mca_dump_state = CLEAR;
	84
0c530ab8 A	85	static void
	86	mca_get_availability(void)
	87	{
	88	uint64_t features = cpuid_info()->cpuid_features;
bd504ef0 A	89	uint32_t family = cpuid_info()->cpuid_family;
	90	uint32_t model = cpuid_info()->cpuid_model;
	91	uint32_t stepping = cpuid_info()->cpuid_stepping;
0c530ab8	92
bd504ef0 A	93	if ((model == CPUID_MODEL_HASWELL && stepping < 3) \|\|
	94	(model == CPUID_MODEL_HASWELL_ULT && stepping < 1) \|\|
	95	(model == CPUID_MODEL_CRYSTALWELL && stepping < 1))
	96	panic("Haswell pre-C0 steppings are not supported");
	97
39236c6e A	98	mca_MCE_present = (features & CPUID_FEATURE_MCE) != 0;
	99	mca_MCA_present = (features & CPUID_FEATURE_MCA) != 0;
	100	mca_family = family;
	101
0c530ab8 A	102	/*
	103	* If MCA, the number of banks etc is reported by the IA32_MCG_CAP MSR.
	104	*/
	105	if (mca_MCA_present) {
	106	ia32_mcg_cap.u64 = rdmsr64(IA32_MCG_CAP);
	107	mca_error_bank_count = ia32_mcg_cap.bits.count;
	108	mca_control_MSR_present = ia32_mcg_cap.bits.mcg_ctl_p;
c910b4d9	109	mca_cmci_present = ia32_mcg_cap.bits.mcg_ext_corr_err_p;
0c530ab8 A	110	}
	111	}
	112
	113	void
	114	mca_cpu_init(void)
	115	{
	116	unsigned int i;
	117
	118	/*
	119	* The first (boot) processor is responsible for discovering the
	120	* machine check architecture present on this machine.
	121	*/
	122	if (!mca_initialized) {
	123	mca_get_availability();
	124	mca_initialized = TRUE;
2d21ac55	125	simple_lock_init(&mca_lock, 0);
0c530ab8 A	126	}
	127
	128	if (mca_MCA_present) {
	129
	130	/* Enable all MCA features */
	131	if (mca_control_MSR_present)
	132	wrmsr64(IA32_MCG_CTL, IA32_MCG_CTL_ENABLE);
	133
2d21ac55	134	switch (mca_family) {
0c530ab8 A	135	case 0x06:
	136	/* Enable all but mc0 */
	137	for (i = 1; i < mca_error_bank_count; i++)
	138	wrmsr64(IA32_MCi_CTL(i),0xFFFFFFFFFFFFFFFFULL);
	139
	140	/* Clear all errors */
	141	for (i = 0; i < mca_error_bank_count; i++)
	142	wrmsr64(IA32_MCi_STATUS(i), 0ULL);
	143	break;
	144	case 0x0F:
	145	/* Enable all banks */
	146	for (i = 0; i < mca_error_bank_count; i++)
	147	wrmsr64(IA32_MCi_CTL(i),0xFFFFFFFFFFFFFFFFULL);
	148
	149	/* Clear all errors */
	150	for (i = 0; i < mca_error_bank_count; i++)
	151	wrmsr64(IA32_MCi_STATUS(i), 0ULL);
	152	break;
	153	}
	154	}
	155
	156	/* Enable machine check exception handling if available */
	157	if (mca_MCE_present) {
	158	set_cr4(get_cr4()\|CR4_MCE);
	159	}
	160	}
	161
c910b4d9 A	162	boolean_t
	163	mca_is_cmci_present(void)
	164	{
	165	if (!mca_initialized)
	166	mca_cpu_init();
	167	return mca_cmci_present;
	168	}
	169
2d21ac55 A	170	void
	171	mca_cpu_alloc(cpu_data_t *cdp)
	172	{
	173	vm_size_t mca_state_size;
	174
	175	/*
	176	* Allocate space for an array of error banks.
	177	*/
	178	mca_state_size = sizeof(mca_state_t) +
	179	sizeof(mca_mci_bank_t) * mca_error_bank_count;
	180	cdp->cpu_mca_state = kalloc(mca_state_size);
	181	if (cdp->cpu_mca_state == NULL) {
	182	printf("mca_cpu_alloc() failed for cpu %d\n", cdp->cpu_number);
	183	return;
	184	}
	185	bzero((void *) cdp->cpu_mca_state, mca_state_size);
	186
	187	/*
	188	* If the boot processor is yet have its allocation made,
	189	* do this now.
	190	*/
	191	if (cpu_datap(master_cpu)->cpu_mca_state == NULL)
	192	mca_cpu_alloc(cpu_datap(master_cpu));
	193	}
	194
	195	static void
593a1d5f	196	mca_save_state(mca_state_t *mca_state)
2d21ac55	197	{
2d21ac55 A	198	mca_mci_bank_t *bank;
	199	unsigned int i;
	200
	201	assert(!ml_get_interrupts_enabled() \|\| get_preemption_level() > 0);
	202
2d21ac55 A	203	if (mca_state == NULL)
	204	return;
	205
	206	mca_state->mca_mcg_ctl = mca_control_MSR_present ?
	207	rdmsr64(IA32_MCG_CTL) : 0ULL;
	208	mca_state->mca_mcg_status.u64 = rdmsr64(IA32_MCG_STATUS);
	209
	210	bank = (mca_mci_bank_t *) &mca_state->mca_error_bank[0];
	211	for (i = 0; i < mca_error_bank_count; i++, bank++) {
	212	bank->mca_mci_ctl = rdmsr64(IA32_MCi_CTL(i));
	213	bank->mca_mci_status.u64 = rdmsr64(IA32_MCi_STATUS(i));
	214	if (!bank->mca_mci_status.bits.val)
	215	continue;
	216	bank->mca_mci_misc = (bank->mca_mci_status.bits.miscv)?
	217	rdmsr64(IA32_MCi_MISC(i)) : 0ULL;
	218	bank->mca_mci_addr = (bank->mca_mci_status.bits.addrv)?
	219	rdmsr64(IA32_MCi_ADDR(i)) : 0ULL;
316670eb	220	mca_state->mca_is_valid = TRUE;
2d21ac55	221	}
c910b4d9 A	222
	223	/*
	224	* If we're the first thread with MCA state, point our package to it
	225	* and don't care about races
	226	*/
	227	if (x86_package()->mca_state == NULL)
15129b1c	228	x86_package()->mca_state = mca_state;
316670eb A	229
316670eb A	230	mca_state->mca_is_saved = TRUE;
2d21ac55 A	231	}
	232
	233	void
	234	mca_check_save(void)
	235	{
593a1d5f A	236	if (mca_dump_state > CLEAR)
593a1d5f A	237	mca_save_state(current_cpu_datap()->cpu_mca_state);
2d21ac55 A	238	}
2d21ac55 A	239
cf7d32b8 A	240	static void
	241	mca_report_cpu_info(void)
	242	{
cf7d32b8 A	243	i386_cpu_info_t *infop = cpuid_info();
cf7d32b8 A	244
5ba3f43e	245	paniclog_append_noflush(" family: %d model: %d stepping: %d microcode: %d\n",
cf7d32b8 A	246	infop->cpuid_family,
	247	infop->cpuid_model,
	248	infop->cpuid_stepping,
6d2010ae	249	infop->cpuid_microcode_version);
5ba3f43e	250	paniclog_append_noflush(" signature: 0x%x\n",
15129b1c	251	infop->cpuid_signature);
5ba3f43e	252	paniclog_append_noflush(" %s\n",
15129b1c	253	infop->cpuid_brand_string);
c910b4d9	254
c910b4d9 A	255	}
c910b4d9 A	256
0c530ab8	257	static void
593a1d5f	258	mca_dump_bank(mca_state_t *state, int i)
0c530ab8	259	{
593a1d5f	260	mca_mci_bank_t *bank;
0c530ab8 A	261	ia32_mci_status_t status;
0c530ab8 A	262
593a1d5f A	263	bank = &state->mca_error_bank[i];
593a1d5f A	264	status = bank->mca_mci_status;
593a1d5f A	265	if (!status.bits.val)
	266	return;
	267
5ba3f43e	268	paniclog_append_noflush(" IA32_MC%d_STATUS(0x%x): 0x%016qx\n",
15129b1c A	269	i, IA32_MCi_STATUS(i), status.u64);
15129b1c A	270
593a1d5f	271	if (status.bits.addrv)
5ba3f43e	272	paniclog_append_noflush(" IA32_MC%d_ADDR(0x%x): 0x%016qx\n",
593a1d5f	273	i, IA32_MCi_ADDR(i), bank->mca_mci_addr);
15129b1c	274
593a1d5f	275	if (status.bits.miscv)
5ba3f43e	276	paniclog_append_noflush(" IA32_MC%d_MISC(0x%x): 0x%016qx\n",
593a1d5f A	277	i, IA32_MCi_MISC(i), bank->mca_mci_misc);
	278	}
	279
	280	static void
316670eb	281	mca_cpu_dump_error_banks(mca_state_t *state)
593a1d5f A	282	{
	283	unsigned int i;
	284
316670eb A	285	if (!state->mca_is_valid)
	286	return;
	287
593a1d5f A	288	for (i = 0; i < mca_error_bank_count; i++ ) {
593a1d5f A	289	mca_dump_bank(state, i);
0c530ab8 A	290	}
	291	}
	292
	293	void
	294	mca_dump(void)
	295	{
316670eb A	296	mca_state_t *mca_state = current_cpu_datap()->cpu_mca_state;
	297	uint64_t deadline;
	298	unsigned int i = 0;
0c530ab8	299
593a1d5f A	300	/*
	301	* Capture local MCA registers to per-cpu data.
	302	*/
	303	mca_save_state(mca_state);
2d21ac55	304
4a3eedf9	305	/*
316670eb	306	* Serialize: the first caller controls dumping MCA registers,
593a1d5f	307	* other threads spin meantime.
4a3eedf9	308	*/
2d21ac55	309	simple_lock(&mca_lock);
593a1d5f	310	if (mca_dump_state > CLEAR) {
4a3eedf9	311	simple_unlock(&mca_lock);
593a1d5f A	312	while (mca_dump_state == DUMPING)
593a1d5f A	313	cpu_pause();
4a3eedf9 A	314	return;
4a3eedf9 A	315	}
593a1d5f A	316	mca_dump_state = DUMPING;
593a1d5f A	317	simple_unlock(&mca_lock);
2d21ac55	318
316670eb A	319	/*
	320	* Wait for all other hardware threads to save their state.
	321	* Or timeout.
	322	*/
	323	deadline = mach_absolute_time() + LockTimeOut;
	324	while (mach_absolute_time() < deadline && i < real_ncpus) {
	325	if (!cpu_datap(i)->cpu_mca_state->mca_is_saved) {
	326	cpu_pause();
	327	continue;
	328	}
	329	i += 1;
	330	}
	331
0c530ab8 A	332	/*
	333	* Report machine-check capabilities:
	334	*/
5ba3f43e	335	paniclog_append_noflush("Machine-check capabilities: 0x%016qx\n", ia32_mcg_cap.u64);
cf7d32b8 A	336
	337	mca_report_cpu_info();
	338
5ba3f43e	339	paniclog_append_noflush(" %d error-reporting banks\n", mca_error_bank_count);
0c530ab8 A	340
0c530ab8 A	341	/*
316670eb	342	* Dump all processor state:
0c530ab8	343	*/
316670eb A	344	for (i = 0; i < real_ncpus; i++) {
	345	mca_state_t *mcsp = cpu_datap(i)->cpu_mca_state;
	346	ia32_mcg_status_t status;
	347
316670eb A	348	if (mcsp == NULL \|\|
316670eb A	349	mcsp->mca_is_saved == FALSE \|\|
15129b1c A	350	mcsp->mca_mcg_status.u64 == 0 \|\|
15129b1c A	351	!mcsp->mca_is_valid) {
316670eb A	352	continue;
	353	}
	354	status = mcsp->mca_mcg_status;
5ba3f43e	355	paniclog_append_noflush("Processor %d: IA32_MCG_STATUS: 0x%016qx\n",
15129b1c	356	i, status.u64);
316670eb A	357	mca_cpu_dump_error_banks(mcsp);
316670eb A	358	}
0c530ab8	359
593a1d5f A	360	/* Update state to release any other threads. */
593a1d5f A	361	mca_dump_state = DUMPED;
0c530ab8	362	}
316670eb A	363
316670eb A	364
39037602	365	#if DEVELOPMENT \|\| DEBUG
316670eb	366	extern void mca_exception_panic(void);
15129b1c	367	extern void lapic_trigger_MC(void);
316670eb A	368	void mca_exception_panic(void)
316670eb A	369	{
15129b1c	370	lapic_trigger_MC();
316670eb	371	}
39037602	372	#endif