[apple/xnu.git] / osfmk / ppc / commpage / bzero_32.s

/*
 * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */

#include <sys/appleapiopts.h>
#include <ppc/asm.h>
#include <machine/cpu_capabilities.h>
#include <machine/commpage.h>

        .text
        .align	2
        

// *******************
// * B Z E R O _ 3 2 *
// *******************
//
// For 32-bit processors with a 32-byte cache line.
//
// Register use:
//		r0 = zero
//		r3 = original ptr, not changed since memset returns it
//		r4 = count of bytes to set
//		r9 = working operand ptr
// We do not touch r2 and r10-r12, which some callers depend on.

        .align	5
bzero_32:						// void	bzero(void *b, size_t len);
        cmplwi	cr7,r4,32		// too short for DCBZ?
        li		r0,0			// get a 0
        neg		r5,r3			// start to compute #bytes to align
        mr		r9,r3			// make copy of operand ptr (can't change r3)
        blt		cr7,Ltail		// length < 32, too short for DCBZ

// At least 32 bytes long, so compute alignment and #cache blocks.

        andi.	r5,r5,0x1F		// r5 <-  #bytes to 32-byte align
        sub		r4,r4,r5		// adjust length
        srwi	r8,r4,5			// r8 <- #32-byte chunks
        cmpwi	cr1,r8,0		// any chunks?
        mtctr	r8				// set up loop count
        beq		1f				// skip if already 32-byte aligned (r8!=0)
        
// 32-byte align.  We just store 32 0s, rather than test and use conditional
// branches.  We've already stored the first few bytes above.

        stw		r0,0(r9)
        stw		r0,4(r9)
        stw		r0,8(r9)
        stw		r0,12(r9)
        stw		r0,16(r9)
        stw		r0,20(r9)
        stw		r0,24(r9)
        stw		r0,28(r9)
        add		r9,r9,r5		// now rp is 32-byte aligned
        beq		cr1,Ltail		// skip if no 32-byte chunks

// Loop doing 32-byte version of DCBZ instruction.
// NB: we take alignment exceptions on cache-inhibited memory.
// The kernel could be changed to zero cr7 when emulating a
// dcbz (as it does on 64-bit processors), so we could avoid all
// but the first.

1:
        andi.	r5,r4,0x1F		// will there be trailing bytes?
        b		2f
        .align	4
2:
        dcbz	0,r9			// zero another 32 bytes
        addi	r9,r9,32
        bdnz	2b
        
        beqlr					// no trailing bytes

// Store trailing bytes.

Ltail:
        andi.	r5,r4,0x10		// test bit 27 separately
        mtcrf	0x01,r4			// remaining byte count to cr7
        
        beq		2f				// no 16-byte chunks
        stw		r0,0(r9)
        stw		r0,4(r9)
        stw		r0,8(r9)
        stw		r0,12(r9)
        addi	r9,r9,16
2:
        bf		28,4f			// 8-byte chunk?
        stw		r0,0(r9)
        stw		r0,4(r9)
        addi	r9,r9,8
4:
        bf		29,5f			// word?
        stw		r0,0(r9)
        addi	r9,r9,4
5:
        bf		30,6f			// halfword?
        sth		r0,0(r9)
        addi	r9,r9,2
6:
        bflr	31				// byte?
        stb		r0,0(r9)
        blr

	COMMPAGE_DESCRIPTOR(bzero_32,_COMM_PAGE_BZERO,kCache32,0,kCommPage32)
Commit	Line	Data
55e303ae A	1	/*
	2	* Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
	3	*
2d21ac55	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
55e303ae	5	*
2d21ac55 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
8f6c56a5	14	*
2d21ac55 A	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5 A	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
8f6c56a5 A	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55 A	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
8f6c56a5	25	*
2d21ac55	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
55e303ae A	27	*/
55e303ae A	28
55e303ae A	29	#include <sys/appleapiopts.h>
	30	#include <ppc/asm.h>
	31	#include <machine/cpu_capabilities.h>
	32	#include <machine/commpage.h>
	33
	34	.text
	35	.align 2
55e303ae A	36
	37
	38	// *******************
	39	// * B Z E R O _ 3 2 *
	40	// *******************
	41	//
	42	// For 32-bit processors with a 32-byte cache line.
	43	//
	44	// Register use:
	45	// r0 = zero
	46	// r3 = original ptr, not changed since memset returns it
	47	// r4 = count of bytes to set
	48	// r9 = working operand ptr
	49	// We do not touch r2 and r10-r12, which some callers depend on.
	50
	51	.align 5
	52	bzero_32: // void bzero(void *b, size_t len);
	53	cmplwi cr7,r4,32 // too short for DCBZ?
	54	li r0,0 // get a 0
	55	neg r5,r3 // start to compute #bytes to align
	56	mr r9,r3 // make copy of operand ptr (can't change r3)
	57	blt cr7,Ltail // length < 32, too short for DCBZ
	58
	59	// At least 32 bytes long, so compute alignment and #cache blocks.
	60
	61	andi. r5,r5,0x1F // r5 <- #bytes to 32-byte align
	62	sub r4,r4,r5 // adjust length
	63	srwi r8,r4,5 // r8 <- #32-byte chunks
	64	cmpwi cr1,r8,0 // any chunks?
	65	mtctr r8 // set up loop count
	66	beq 1f // skip if already 32-byte aligned (r8!=0)
	67
	68	// 32-byte align. We just store 32 0s, rather than test and use conditional
	69	// branches. We've already stored the first few bytes above.
	70
	71	stw r0,0(r9)
	72	stw r0,4(r9)
	73	stw r0,8(r9)
	74	stw r0,12(r9)
	75	stw r0,16(r9)
	76	stw r0,20(r9)
	77	stw r0,24(r9)
	78	stw r0,28(r9)
	79	add r9,r9,r5 // now rp is 32-byte aligned
	80	beq cr1,Ltail // skip if no 32-byte chunks
	81
	82	// Loop doing 32-byte version of DCBZ instruction.
	83	// NB: we take alignment exceptions on cache-inhibited memory.
	84	// The kernel could be changed to zero cr7 when emulating a
	85	// dcbz (as it does on 64-bit processors), so we could avoid all
	86	// but the first.
	87
	88	1:
	89	andi. r5,r4,0x1F // will there be trailing bytes?
	90	b 2f
	91	.align 4
	92	2:
	93	dcbz 0,r9 // zero another 32 bytes
	94	addi r9,r9,32
	95	bdnz 2b
	96
	97	beqlr // no trailing bytes
	98
	99	// Store trailing bytes.
100
101	Ltail:
102	andi. r5,r4,0x10 // test bit 27 separately
103	mtcrf 0x01,r4 // remaining byte count to cr7
104
105	beq 2f // no 16-byte chunks
106	stw r0,0(r9)
107	stw r0,4(r9)
108	stw r0,8(r9)
109	stw r0,12(r9)
110	addi r9,r9,16
111	2:
112	bf 28,4f // 8-byte chunk?
113	stw r0,0(r9)
114	stw r0,4(r9)
115	addi r9,r9,8
116	4:
117	bf 29,5f // word?
118	stw r0,0(r9)
119	addi r9,r9,4
120	5:
121	bf 30,6f // halfword?
122	sth r0,0(r9)
123	addi r9,r9,2
124	6:
125	bflr 31 // byte?
126	stb r0,0(r9)
127	blr
128
91447636	129	COMMPAGE_DESCRIPTOR(bzero_32,_COMM_PAGE_BZERO,kCache32,0,kCommPage32)