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b0d623f7 1/*
39236c6e 2 * Copyright (c) 2000-2013 Apple Inc. All rights reserved.
b0d623f7
A
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28/*
29 * @OSF_COPYRIGHT@
30 */
31/*
32 * Mach Operating System
33 * Copyright (c) 1991,1990,1989 Carnegie Mellon University
34 * All Rights Reserved.
35 *
36 * Permission to use, copy, modify and distribute this software and its
37 * documentation is hereby granted, provided that both the copyright
38 * notice and this permission notice appear in all copies of the
39 * software, derivative works or modified versions, and any portions
40 * thereof, and that both notices appear in supporting documentation.
41 *
42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
45 *
46 * Carnegie Mellon requests users of this software to return to
47 *
48 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
49 * School of Computer Science
50 * Carnegie Mellon University
51 * Pittsburgh PA 15213-3890
52 *
53 * any improvements or extensions that they make and grant Carnegie Mellon
54 * the rights to redistribute these changes.
55 */
56/*
57 */
58#include <mach_assert.h>
59
60#include <string.h>
61#include <mach/boolean.h>
62#include <mach/i386/vm_types.h>
63#include <mach/i386/vm_param.h>
64#include <kern/kern_types.h>
65#include <kern/misc_protos.h>
66#include <sys/errno.h>
67#include <i386/param.h>
68#include <i386/misc_protos.h>
69#include <i386/cpu_data.h>
70#include <i386/machine_routines.h>
71#include <i386/cpuid.h>
72#include <i386/vmx.h>
73#include <vm/pmap.h>
74#include <vm/vm_map.h>
75#include <vm/vm_kern.h>
76#include <vm/vm_fault.h>
77
78#include <libkern/OSAtomic.h>
79#include <sys/kdebug.h>
80
39236c6e
A
81#if !MACH_KDP
82#include <kdp/kdp_callout.h>
83#endif /* !MACH_KDP */
84
3e170ce0
A
85#include <libkern/OSDebug.h>
86#if CONFIG_DTRACE
87#include <mach/sdt.h>
88#endif
89
b0d623f7
A
90#if 0
91
92#undef KERNEL_DEBUG
93#define KERNEL_DEBUG KERNEL_DEBUG_CONSTANT
94#define KDEBUG 1
95
96#endif
97
98/* XXX - should be gone from here */
99extern void invalidate_icache64(addr64_t addr, unsigned cnt, int phys);
100extern void flush_dcache64(addr64_t addr, unsigned count, int phys);
101extern boolean_t phys_page_exists(ppnum_t);
102extern void bcopy_no_overwrite(const char *from, char *to,vm_size_t bytes);
103extern void pmap_set_reference(ppnum_t pn);
104extern void mapping_set_mod(ppnum_t pa);
105extern void mapping_set_ref(ppnum_t pn);
106
107extern void ovbcopy(const char *from,
108 char *to,
109 vm_size_t nbytes);
39236c6e 110void machine_callstack(uintptr_t *buf, vm_size_t callstack_max);
b0d623f7
A
111
112
113#define value_64bit(value) ((value) & 0xFFFFFFFF00000000ULL)
114#define low32(x) ((unsigned int)((x) & 0x00000000FFFFFFFFULL))
115
116#define INT_SIZE (BYTE_SIZE * sizeof (int))
117
118/*
119 * Set indicated bit in bit string.
120 */
121void
122setbit(int bitno, int *s)
123{
124 s[bitno / INT_SIZE] |= 1 << (bitno % INT_SIZE);
125}
126
127/*
128 * Clear indicated bit in bit string.
129 */
130void
131clrbit(int bitno, int *s)
132{
133 s[bitno / INT_SIZE] &= ~(1 << (bitno % INT_SIZE));
134}
135
136/*
137 * Test if indicated bit is set in bit string.
138 */
139int
140testbit(int bitno, int *s)
141{
142 return s[bitno / INT_SIZE] & (1 << (bitno % INT_SIZE));
143}
144
145/*
146 * Find first bit set in bit string.
147 */
148int
149ffsbit(int *s)
150{
151 int offset;
152
153 for (offset = 0; !*s; offset += (int)INT_SIZE, ++s);
154 return offset + __builtin_ctz(*s);
155}
156
157int
158ffs(unsigned int mask)
159{
160 if (mask == 0)
161 return 0;
162
163 /*
164 * NOTE: cannot use __builtin_ffs because it generates a call to
165 * 'ffs'
166 */
167 return 1 + __builtin_ctz(mask);
168}
169
170void
171bzero_phys_nc(
172 addr64_t src64,
173 uint32_t bytes)
174{
175 bzero_phys(src64,bytes);
176}
177
178void
179bzero_phys(
180 addr64_t src64,
181 uint32_t bytes)
182{
183 bzero(PHYSMAP_PTOV(src64), bytes);
184}
185
186
187/*
188 * bcopy_phys - like bcopy but copies from/to physical addresses.
189 */
190
191void
192bcopy_phys(
193 addr64_t src64,
194 addr64_t dst64,
195 vm_size_t bytes)
196{
197 /* Not necessary for K64 - but ensure we stay within a page */
198 if (((((uint32_t)src64 & (NBPG-1)) + bytes) > NBPG) ||
199 ((((uint32_t)dst64 & (NBPG-1)) + bytes) > NBPG) ) {
200 panic("bcopy_phys alignment");
201 }
202 bcopy(PHYSMAP_PTOV(src64), PHYSMAP_PTOV(dst64), bytes);
203}
204
6d2010ae
A
205/*
206 * allow a function to get a quick virtual mapping of a physical page
207 */
208
209int
210apply_func_phys(
211 addr64_t dst64,
212 vm_size_t bytes,
213 int (*func)(void * buffer, vm_size_t bytes, void * arg),
214 void * arg)
215{
216 /* Not necessary for K64 - but ensure we stay within a page */
217 if (((((uint32_t)dst64 & (NBPG-1)) + bytes) > NBPG) ) {
218 panic("apply_func_phys alignment");
219 }
220
221 return func(PHYSMAP_PTOV(dst64), bytes, arg);
222}
223
b0d623f7
A
224/*
225 * ovbcopy - like bcopy, but recognizes overlapping ranges and handles
226 * them correctly.
227 */
228
229void
230ovbcopy(
231 const char *from,
232 char *to,
233 vm_size_t bytes) /* num bytes to copy */
234{
235 /* Assume that bcopy copies left-to-right (low addr first). */
236 if (from + bytes <= to || to + bytes <= from || to == from)
237 bcopy_no_overwrite(from, to, bytes); /* non-overlapping or no-op*/
238 else if (from > to)
239 bcopy_no_overwrite(from, to, bytes); /* overlapping but OK */
240 else {
241 /* to > from: overlapping, and must copy right-to-left. */
242 from += bytes - 1;
243 to += bytes - 1;
244 while (bytes-- > 0)
245 *to-- = *from--;
246 }
247}
248
249
250/*
251 * Read data from a physical address. Memory should not be cache inhibited.
252 */
253
3e170ce0
A
254uint64_t reportphyreaddelayabs;
255uint32_t reportphyreadosbt;
b0d623f7 256
6d2010ae 257static inline unsigned int
b0d623f7
A
258ml_phys_read_data(pmap_paddr_t paddr, int size)
259{
39236c6e 260 unsigned int result = 0;
fe8ab488
A
261 unsigned char s1;
262 unsigned short s2;
3e170ce0
A
263 boolean_t istate;
264 uint64_t sabs, eabs;
b0d623f7 265
3e170ce0 266 if (__improbable(!physmap_enclosed(paddr)))
7ddcb079
A
267 panic("%s: 0x%llx out of bounds\n", __FUNCTION__, paddr);
268
3e170ce0
A
269 if (__improbable(reportphyreaddelayabs != 0)) {
270 istate = ml_set_interrupts_enabled(FALSE);
271 sabs = mach_absolute_time();
272 }
273
b0d623f7 274 switch (size) {
b0d623f7 275 case 1:
7ddcb079
A
276 s1 = *(volatile unsigned char *)PHYSMAP_PTOV(paddr);
277 result = s1;
278 break;
b0d623f7 279 case 2:
7ddcb079
A
280 s2 = *(volatile unsigned short *)PHYSMAP_PTOV(paddr);
281 result = s2;
282 break;
b0d623f7 283 case 4:
7ddcb079
A
284 result = *(volatile unsigned int *)PHYSMAP_PTOV(paddr);
285 break;
286 default:
287 panic("Invalid size %d for ml_phys_read_data\n", size);
288 break;
b0d623f7 289 }
3e170ce0
A
290
291 if (__improbable(reportphyreaddelayabs != 0)) {
292 eabs = mach_absolute_time();
293 (void)ml_set_interrupts_enabled(istate);
294
295 if ((eabs - sabs) > reportphyreaddelayabs) {
296 if (reportphyreadosbt) {
297 OSReportWithBacktrace("ml_phys_read_data took %lluus\n", (eabs - sabs) / 1000);
298 }
299#if CONFIG_DTRACE
300 DTRACE_PHYSLAT3(physread, uint64_t, (eabs - sabs),
301 pmap_paddr_t, paddr, uint32_t, size);
302#endif
303 }
304 }
305
b0d623f7
A
306 return result;
307}
308
309static unsigned long long
310ml_phys_read_long_long(pmap_paddr_t paddr )
311{
7ddcb079
A
312 if (!physmap_enclosed(paddr))
313 panic("%s: 0x%llx out of bounds\n", __FUNCTION__, paddr);
314 return *(volatile unsigned long long *)PHYSMAP_PTOV(paddr);
b0d623f7
A
315}
316
b0d623f7
A
317unsigned int ml_phys_read( vm_offset_t paddr)
318{
319 return ml_phys_read_data((pmap_paddr_t)paddr, 4);
320}
321
322unsigned int ml_phys_read_word(vm_offset_t paddr) {
323
324 return ml_phys_read_data((pmap_paddr_t)paddr, 4);
325}
326
327unsigned int ml_phys_read_64(addr64_t paddr64)
328{
329 return ml_phys_read_data((pmap_paddr_t)paddr64, 4);
330}
331
332unsigned int ml_phys_read_word_64(addr64_t paddr64)
333{
334 return ml_phys_read_data((pmap_paddr_t)paddr64, 4);
335}
336
337unsigned int ml_phys_read_half(vm_offset_t paddr)
338{
339 return ml_phys_read_data((pmap_paddr_t)paddr, 2);
340}
341
342unsigned int ml_phys_read_half_64(addr64_t paddr64)
343{
344 return ml_phys_read_data((pmap_paddr_t)paddr64, 2);
345}
346
347unsigned int ml_phys_read_byte(vm_offset_t paddr)
348{
349 return ml_phys_read_data((pmap_paddr_t)paddr, 1);
350}
351
352unsigned int ml_phys_read_byte_64(addr64_t paddr64)
353{
354 return ml_phys_read_data((pmap_paddr_t)paddr64, 1);
355}
356
357unsigned long long ml_phys_read_double(vm_offset_t paddr)
358{
359 return ml_phys_read_long_long((pmap_paddr_t)paddr);
360}
361
362unsigned long long ml_phys_read_double_64(addr64_t paddr64)
363{
364 return ml_phys_read_long_long((pmap_paddr_t)paddr64);
365}
366
367
368
369/*
370 * Write data to a physical address. Memory should not be cache inhibited.
371 */
372
6d2010ae 373static inline void
b0d623f7
A
374ml_phys_write_data(pmap_paddr_t paddr, unsigned long data, int size)
375{
7ddcb079
A
376 if (!physmap_enclosed(paddr))
377 panic("%s: 0x%llx out of bounds\n", __FUNCTION__, paddr);
378
b0d623f7
A
379 switch (size) {
380 case 1:
7ddcb079 381 *(volatile unsigned char *)PHYSMAP_PTOV(paddr) = (unsigned char)data;
b0d623f7
A
382 break;
383 case 2:
7ddcb079 384 *(volatile unsigned short *)PHYSMAP_PTOV(paddr) = (unsigned short)data;
b0d623f7
A
385 break;
386 case 4:
7ddcb079 387 *(volatile unsigned int *)PHYSMAP_PTOV(paddr) = (unsigned int)data;
b0d623f7 388 break;
7ddcb079
A
389 default:
390 panic("Invalid size %d for ml_phys_write_data\n", size);
391 break;
b0d623f7
A
392 }
393}
394
395static void
396ml_phys_write_long_long(pmap_paddr_t paddr, unsigned long long data)
397{
7ddcb079
A
398 if (!physmap_enclosed(paddr))
399 panic("%s: 0x%llx out of bounds\n", __FUNCTION__, paddr);
400
401 *(volatile unsigned long long *)PHYSMAP_PTOV(paddr) = data;
b0d623f7
A
402}
403
b0d623f7
A
404void ml_phys_write_byte(vm_offset_t paddr, unsigned int data)
405{
406 ml_phys_write_data((pmap_paddr_t)paddr, data, 1);
407}
408
409void ml_phys_write_byte_64(addr64_t paddr64, unsigned int data)
410{
411 ml_phys_write_data((pmap_paddr_t)paddr64, data, 1);
412}
413
414void ml_phys_write_half(vm_offset_t paddr, unsigned int data)
415{
416 ml_phys_write_data((pmap_paddr_t)paddr, data, 2);
417}
418
419void ml_phys_write_half_64(addr64_t paddr64, unsigned int data)
420{
421 ml_phys_write_data((pmap_paddr_t)paddr64, data, 2);
422}
423
424void ml_phys_write(vm_offset_t paddr, unsigned int data)
425{
426 ml_phys_write_data((pmap_paddr_t)paddr, data, 4);
427}
428
429void ml_phys_write_64(addr64_t paddr64, unsigned int data)
430{
431 ml_phys_write_data((pmap_paddr_t)paddr64, data, 4);
432}
433
434void ml_phys_write_word(vm_offset_t paddr, unsigned int data)
435{
436 ml_phys_write_data((pmap_paddr_t)paddr, data, 4);
437}
438
439void ml_phys_write_word_64(addr64_t paddr64, unsigned int data)
440{
441 ml_phys_write_data((pmap_paddr_t)paddr64, data, 4);
442}
443
444void ml_phys_write_double(vm_offset_t paddr, unsigned long long data)
445{
446 ml_phys_write_long_long((pmap_paddr_t)paddr, data);
447}
448
449void ml_phys_write_double_64(addr64_t paddr64, unsigned long long data)
450{
451 ml_phys_write_long_long((pmap_paddr_t)paddr64, data);
452}
453
454
455/* PCI config cycle probing
456 *
457 *
458 * Read the memory location at physical address paddr.
7ddcb079
A
459 * *Does not* recover from machine checks, unlike the PowerPC implementation.
460 * Should probably be deprecated.
b0d623f7
A
461 */
462
463boolean_t
464ml_probe_read(vm_offset_t paddr, unsigned int *val)
465{
466 if ((PAGE_SIZE - (paddr & PAGE_MASK)) < 4)
467 return FALSE;
468
469 *val = ml_phys_read((pmap_paddr_t)paddr);
470
471 return TRUE;
472}
473
474/*
475 * Read the memory location at physical address paddr.
476 * This is a part of a device probe, so there is a good chance we will
477 * have a machine check here. So we have to be able to handle that.
478 * We assume that machine checks are enabled both in MSR and HIDs
479 */
480boolean_t
481ml_probe_read_64(addr64_t paddr64, unsigned int *val)
482{
483 if ((PAGE_SIZE - (paddr64 & PAGE_MASK)) < 4)
484 return FALSE;
485
486 *val = ml_phys_read_64((pmap_paddr_t)paddr64);
487 return TRUE;
488}
489
490
491int bcmp(
492 const void *pa,
493 const void *pb,
494 size_t len)
495{
496 const char *a = (const char *)pa;
497 const char *b = (const char *)pb;
498
499 if (len == 0)
500 return 0;
501
502 do
503 if (*a++ != *b++)
504 break;
505 while (--len);
506
507 return (int)len;
508}
509
510int
511memcmp(const void *s1, const void *s2, size_t n)
512{
513 if (n != 0) {
514 const unsigned char *p1 = s1, *p2 = s2;
515
516 do {
517 if (*p1++ != *p2++)
518 return (*--p1 - *--p2);
519 } while (--n != 0);
520 }
521 return (0);
522}
523
fe8ab488
A
524void *
525memmove(void *dst, const void *src, size_t ulen)
526{
527 bcopy(src, dst, ulen);
528 return dst;
529}
530
b0d623f7
A
531/*
532 * Abstract:
533 * strlen returns the number of characters in "string" preceeding
534 * the terminating null character.
535 */
536
537size_t
538strlen(
539 register const char *string)
540{
541 register const char *ret = string;
542
543 while (*string++ != '\0')
544 continue;
545 return string - 1 - ret;
546}
547
548uint32_t
549hw_compare_and_store(uint32_t oldval, uint32_t newval, volatile uint32_t *dest)
550{
551 return OSCompareAndSwap((UInt32)oldval,
552 (UInt32)newval,
553 (volatile UInt32 *)dest);
554}
555
556#if MACH_ASSERT
557
558/*
559 * Machine-dependent routine to fill in an array with up to callstack_max
560 * levels of return pc information.
561 */
562void machine_callstack(
39236c6e 563 __unused uintptr_t *buf,
b0d623f7
A
564 __unused vm_size_t callstack_max)
565{
566}
567
568#endif /* MACH_ASSERT */
569
570void fillPage(ppnum_t pa, unsigned int fill)
571{
572 pmap_paddr_t src;
573 int i;
574 int cnt = PAGE_SIZE / sizeof(unsigned int);
575 unsigned int *addr;
576
577 src = i386_ptob(pa);
578 for (i = 0, addr = (unsigned int *)PHYSMAP_PTOV(src); i < cnt; i++)
579 *addr++ = fill;
580}
581
b0d623f7
A
582static inline void __clflush(void *ptr)
583{
584 __asm__ volatile("clflush (%0)" : : "r" (ptr));
585}
586
587void dcache_incoherent_io_store64(addr64_t pa, unsigned int count)
588{
6d2010ae
A
589 addr64_t linesize = cpuid_info()->cache_linesize;
590 addr64_t bound = (pa + count + linesize - 1) & ~(linesize - 1);
b0d623f7 591
39236c6e 592 mfence();
b0d623f7 593
6d2010ae
A
594 while (pa < bound) {
595 __clflush(PHYSMAP_PTOV(pa));
596 pa += linesize;
597 }
b0d623f7 598
39236c6e 599 mfence();
b0d623f7
A
600}
601
602void dcache_incoherent_io_flush64(addr64_t pa, unsigned int count)
603{
604 return(dcache_incoherent_io_store64(pa,count));
605}
606
607void
6d2010ae 608flush_dcache64(addr64_t addr, unsigned count, int phys)
b0d623f7 609{
6d2010ae
A
610 if (phys) {
611 dcache_incoherent_io_flush64(addr, count);
612 }
613 else {
316670eb 614 uint64_t linesize = cpuid_info()->cache_linesize;
6d2010ae 615 addr64_t bound = (addr + count + linesize -1) & ~(linesize - 1);
39236c6e 616 mfence();
6d2010ae
A
617 while (addr < bound) {
618 __clflush((void *) (uintptr_t) addr);
619 addr += linesize;
620 }
39236c6e 621 mfence();
6d2010ae 622 }
b0d623f7
A
623}
624
625void
626invalidate_icache64(__unused addr64_t addr,
627 __unused unsigned count,
628 __unused int phys)
629{
630}
631
632
633addr64_t vm_last_addr;
634
635void
636mapping_set_mod(ppnum_t pn)
637{
638 pmap_set_modify(pn);
639}
640
641void
642mapping_set_ref(ppnum_t pn)
643{
644 pmap_set_reference(pn);
645}
646
39236c6e 647extern i386_cpu_info_t cpuid_cpu_info;
b0d623f7
A
648void
649cache_flush_page_phys(ppnum_t pa)
650{
651 boolean_t istate;
652 unsigned char *cacheline_addr;
39236c6e
A
653 i386_cpu_info_t *cpuid_infop = cpuid_info();
654 int cacheline_size;
655 int cachelines_to_flush;
656
657 cacheline_size = cpuid_infop->cache_linesize;
658 if (cacheline_size == 0)
659 panic("cacheline_size=0 cpuid_infop=%p\n", cpuid_infop);
660 cachelines_to_flush = PAGE_SIZE/cacheline_size;
b0d623f7 661
39236c6e 662 mfence();
b0d623f7
A
663
664 istate = ml_set_interrupts_enabled(FALSE);
665
666 for (cacheline_addr = (unsigned char *)PHYSMAP_PTOV(i386_ptob(pa));
667 cachelines_to_flush > 0;
668 cachelines_to_flush--, cacheline_addr += cacheline_size) {
669 __clflush((void *) cacheline_addr);
670 }
671
672 (void) ml_set_interrupts_enabled(istate);
673
39236c6e 674 mfence();
b0d623f7
A
675}
676
677
b0d623f7
A
678#if !MACH_KDP
679void
39236c6e 680kdp_register_callout(kdp_callout_fn_t fn, void *arg)
b0d623f7 681{
39236c6e 682#pragma unused(fn,arg)
b0d623f7
A
683}
684#endif
685
686#if !CONFIG_VMX
687int host_vmxon(boolean_t exclusive __unused)
688{
689 return VMX_UNSUPPORTED;
690}
691
692void host_vmxoff(void)
693{
694 return;
695}
696#endif