[apple/xnu.git] / osfmk / chud / ppc / chud_cpu_asm.s

/*
 * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */
 
#include <chud/ppc/chud_spr.h>
#include <ppc/asm.h>
#include <mach/kern_return.h>

/*
 * kern_return_t mfspr64(uint64_t *val, int spr);
 * 
 * r3: address to store value in
 * r4: spr to read from
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mfspr64)

EXT(mfspr64):
            ;; generic PPC 64-bit wide SPRs
            cmpwi	r4,chud_ppc_srr0
            beq		mfspr64_srr0
            cmpwi	r4,chud_ppc_srr1
            beq		mfspr64_srr1
            cmpwi	r4,chud_ppc_dar
            beq		mfspr64_dar
            cmpwi	r4,chud_ppc_sdr1
            beq		mfspr64_sdr1
            cmpwi	r4,chud_ppc_sprg0
            beq		mfspr64_sprg0       
            cmpwi	r4,chud_ppc_sprg1
            beq		mfspr64_sprg1  
            cmpwi	r4,chud_ppc_sprg2
            beq		mfspr64_sprg2  
            cmpwi	r4,chud_ppc_sprg3
            beq		mfspr64_sprg3
            cmpwi	r4,chud_ppc64_asr
            beq		mfspr64_asr
            cmpwi	r4,chud_ppc_dabr
            beq		mfspr64_dabr
            
            ;; GPUL specific 64-bit wide SPRs
            cmpwi	r4,chud_970_hid0
            beq		mfspr64_hid0
            cmpwi	r4,chud_970_hid1
            beq		mfspr64_hid1
            cmpwi	r4,chud_970_hid4
            beq		mfspr64_hid4
            cmpwi	r4,chud_970_hid5
            beq		mfspr64_hid5       
            cmpwi	r4,chud_970_mmcr0
            beq		mfspr64_mmcr0            
            cmpwi	r4,chud_970_mmcr1
            beq		mfspr64_mmcr1
            cmpwi	r4,chud_970_mmcra
            beq		mfspr64_mmcra
            cmpwi	r4,chud_970_siar
            beq		mfspr64_siar
            cmpwi	r4,chud_970_sdar
            beq		mfspr64_sdar
            cmpwi	r4,chud_970_imc
            beq		mfspr64_imc
            cmpwi	r4,chud_970_rmor
            beq		mfspr64_rmor
            cmpwi	r4,chud_970_hrmor
            beq		mfspr64_hrmor
            cmpwi	r4,chud_970_hior
            beq		mfspr64_hior
            cmpwi	r4,chud_970_lpidr
            beq		mfspr64_lpidr
            cmpwi	r4,chud_970_lpcr
            beq		mfspr64_lpcr
            cmpwi	r4,chud_970_dabrx
            beq		mfspr64_dabrx
            cmpwi	r4,chud_970_hsprg0
            beq		mfspr64_hsprg0
            cmpwi	r4,chud_970_hsprg1
            beq		mfspr64_hsprg1
            cmpwi	r4,chud_970_hsrr0
            beq		mfspr64_hsrr0
            cmpwi	r4,chud_970_hsrr1
            beq		mfspr64_hsrr1
            cmpwi	r4,chud_970_hdec
            beq		mfspr64_hdec
            cmpwi	r4,chud_970_trig0
            beq		mfspr64_trig0
            cmpwi	r4,chud_970_trig1
            beq		mfspr64_trig1
            cmpwi	r4,chud_970_trig2
            beq		mfspr64_trig2
            cmpwi	r4,chud_ppc64_accr
            beq		mfspr64_accr
            cmpwi	r4,chud_970_scomc
            beq		mfspr64_scomc
            cmpwi	r4,chud_970_scomd
            beq		mfspr64_scomd
                                                                                                                                                            
            b		mfspr64_failure
            
mfspr64_srr0:
            mfspr	r5,chud_ppc_srr0
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_srr1:
            mfspr	r5,chud_ppc_srr1
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_dar:
            mfspr	r5,chud_ppc_dar
            std		r5,0(r3)
            b		mfspr64_success          
mfspr64_sdr1:
            mfspr	r5,chud_ppc_sdr1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg0:
            mfspr	r5,chud_ppc_sprg0
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg1:
            mfspr	r5,chud_ppc_sprg1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg2:
            mfspr	r5,chud_ppc_sprg2
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg3:
            mfspr	r5,chud_ppc_sprg3
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_asr:
            mfspr	r5,chud_ppc64_asr
            std		r5,0(r3)
            b		mfspr64_success             
mfspr64_dabr:
            mfspr	r5,chud_ppc_dabr
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hid0:
            mfspr	r5,chud_970_hid0
            std		r5,0(r3)
            b		mfspr64_success            
mfspr64_hid1:
            mfspr	r5,chud_970_hid1
            std		r5,0(r3)
            b		mfspr64_success     
mfspr64_hid4:
            mfspr	r5,chud_970_hid4
            std		r5,0(r3)
            b		mfspr64_success             
mfspr64_hid5:
            mfspr	r5,chud_970_hid5
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_mmcr0:
            mfspr	r5,chud_970_mmcr0
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_mmcr1:
            mfspr	r5,chud_970_mmcr1
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_mmcra:
            mfspr	r5,chud_970_mmcra
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_siar:
            mfspr	r5,chud_970_siar
            std		r5,0(r3)
            b		mfspr64_success            
mfspr64_sdar:
            mfspr	r5,chud_970_sdar
            std		r5,0(r3)
            b		mfspr64_success              
mfspr64_imc:
            mfspr	r5,chud_970_imc
            std		r5,0(r3)
            b		mfspr64_success                          
mfspr64_rmor:
            mfspr	r5,chud_970_rmor
            std		r5,0(r3)
            b		mfspr64_success              
mfspr64_hrmor:
            mfspr	r5,chud_970_hrmor
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_hior:
            mfspr	r5,chud_970_hior
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_lpidr:
            mfspr	r5,chud_970_lpidr
            std		r5,0(r3)
            b		mfspr64_success   
mfspr64_lpcr:
            mfspr	r5,chud_970_lpcr
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_dabrx:
            mfspr	r5,chud_970_dabrx
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_hsprg0:
            mfspr	r5,chud_970_hsprg0
            std		r5,0(r3)
            b		mfspr64_success   
mfspr64_hsprg1:
            mfspr	r5,chud_970_hsprg1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hsrr0:
            mfspr	r5,chud_970_hsrr0
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hsrr1:
            mfspr	r5,chud_970_hsrr1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hdec:
            mfspr	r5,chud_970_hdec
            std		r5,0(r3)
            b		mfspr64_success             
mfspr64_trig0:
            mfspr	r5,chud_970_trig0
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_trig1:
            mfspr	r5,chud_970_trig1
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_trig2:
            mfspr	r5,chud_970_trig2
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_accr:
            mfspr	r5,chud_ppc64_accr
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_scomc:
            mfspr	r5,chud_970_scomc
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_scomd:
            mfspr	r5,chud_970_scomd
            std		r5,0(r3)
            b		mfspr64_success
            
mfspr64_failure:
            li		r3,KERN_FAILURE
            blr
            
mfspr64_success:
            li		r3,KERN_SUCCESS
            blr


/*
 * kern_return_t mtspr64(int spr, uint64_t *val);
 * 
 * r3: spr to write to
 * r4: address to get value from
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mtspr64)

EXT(mtspr64):
            ;; generic PPC 64-bit wide SPRs
            cmpwi	r3,chud_ppc_srr0
            beq		mtspr64_srr0
            cmpwi	r3,chud_ppc_srr1
            beq		mtspr64_srr1
            cmpwi	r3,chud_ppc_dar
            beq		mtspr64_dar
            cmpwi	r3,chud_ppc_sdr1
            beq		mtspr64_sdr1
            cmpwi	r3,chud_ppc_sprg0
            beq		mtspr64_sprg0       
            cmpwi	r3,chud_ppc_sprg1
            beq		mtspr64_sprg1  
            cmpwi	r3,chud_ppc_sprg2
            beq		mtspr64_sprg2  
            cmpwi	r3,chud_ppc_sprg3
            beq		mtspr64_sprg3
            cmpwi	r3,chud_ppc64_asr
            beq		mtspr64_asr
            cmpwi	r3,chud_ppc_dabr
            beq		mtspr64_dabr
            
            ;; GPUL specific 64-bit wide SPRs
            cmpwi	r3,chud_970_hid0
            beq		mtspr64_hid0
            cmpwi	r3,chud_970_hid1
            beq		mtspr64_hid1
            cmpwi	r3,chud_970_hid4
            beq		mtspr64_hid4
            cmpwi	r3,chud_970_hid5
            beq		mtspr64_hid5       
            cmpwi	r3,chud_970_mmcr0
            beq		mtspr64_mmcr0            
            cmpwi	r3,chud_970_mmcr1
            beq		mtspr64_mmcr1
            cmpwi	r3,chud_970_mmcra
            beq		mtspr64_mmcra
            cmpwi	r3,chud_970_siar
            beq		mtspr64_siar
            cmpwi	r3,chud_970_sdar
            beq		mtspr64_sdar
            cmpwi	r3,chud_970_imc
            beq		mtspr64_imc
            cmpwi	r3,chud_970_rmor
            beq		mtspr64_rmor
            cmpwi	r3,chud_970_hrmor
            beq		mtspr64_hrmor
            cmpwi	r3,chud_970_hior
            beq		mtspr64_hior
            cmpwi	r3,chud_970_lpidr
            beq		mtspr64_lpidr
            cmpwi	r3,chud_970_lpcr
            beq		mtspr64_lpcr
            cmpwi	r3,chud_970_dabrx
            beq		mtspr64_dabrx       
            cmpwi	r3,chud_970_hsprg0
            beq		mtspr64_hsprg0
            cmpwi	r3,chud_970_hsprg1
            beq		mtspr64_hsprg1
            cmpwi	r3,chud_970_hsrr0
            beq		mtspr64_hsrr0
            cmpwi	r3,chud_970_hsrr1
            beq		mtspr64_hsrr1
            cmpwi	r3,chud_970_hdec
            beq		mtspr64_hdec
            cmpwi	r3,chud_970_trig0
            beq		mtspr64_trig0
            cmpwi	r3,chud_970_trig1
            beq		mtspr64_trig1
            cmpwi	r3,chud_970_trig2
            beq		mtspr64_trig2
            cmpwi	r3,chud_ppc64_accr
            beq		mtspr64_accr
            cmpwi	r3,chud_970_scomc
            beq		mtspr64_scomc
            cmpwi	r3,chud_970_scomd
            beq		mtspr64_scomd
                                                                                                                                                            
            b		mtspr64_failure
            
mtspr64_srr0:
            ld		r5,0(r4)
            mtspr	chud_ppc_srr0,r5
            b		mtspr64_success
mtspr64_srr1:
            ld		r5,0(r4)
            mtspr	chud_ppc_srr1,r5
            b		mtspr64_success
mtspr64_dar:
            ld		r5,0(r4)
            mtspr	chud_ppc_dar,r5
            b		mtspr64_success          
mtspr64_sdr1:
            ld		r5,0(r4)
            mtspr	chud_ppc_sdr1,r5
            b		mtspr64_success 
mtspr64_sprg0:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg0,r5
            b		mtspr64_success
mtspr64_sprg1:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg1,r5
            b		mtspr64_success 
mtspr64_sprg2:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg2,r5
            b		mtspr64_success 
mtspr64_sprg3:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg3,r5
            b		mtspr64_success 
mtspr64_asr:
            ld		r5,0(r4)
            mtspr	chud_ppc64_asr,r5
            b		mtspr64_success             
mtspr64_dabr:
            ld		r5,0(r4)
            mtspr	chud_ppc_dabr,r5
            b		mtspr64_success 
mtspr64_hid0:
            ld		r5,0(r4)
            sync
            mtspr	chud_970_hid0,r5
            mfspr	r5,chud_970_hid0	/* syncronization requirements */
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            b		mtspr64_success            
mtspr64_hid1:
            ld		r5,0(r4)
            mtspr	chud_970_hid1,r5	/* tell you twice */
            mtspr	chud_970_hid1,r5
            isync
            b		mtspr64_success     
mtspr64_hid4:
            ld		r5,0(r4)
            sync				/* syncronization requirements */
            mtspr	chud_970_hid4,r5
            isync
            b		mtspr64_success             
mtspr64_hid5:
            ld		r5,0(r4)
            mtspr	chud_970_hid5,r5
            b		mtspr64_success
mtspr64_mmcr0:
            ld		r5,0(r4)
            mtspr	chud_970_mmcr0,r5
            b		mtspr64_success
mtspr64_mmcr1:
            ld		r5,0(r4)
            mtspr	chud_970_mmcr1,r5
            b		mtspr64_success
mtspr64_mmcra:
            ld		r5,0(r4)
            mtspr	chud_970_mmcra,r5
            b		mtspr64_success
mtspr64_siar:
            ld		r5,0(r4)
            mtspr	chud_970_siar,r5
            b		mtspr64_success            
mtspr64_sdar:
            ld		r5,0(r4)
            mtspr	chud_970_sdar,r5
            b		mtspr64_success              
mtspr64_imc:
            ld		r5,0(r4)
            mtspr	chud_970_imc,r5
            b		mtspr64_success                          
mtspr64_rmor:
            ld		r5,0(r4)
            mtspr	chud_970_rmor,r5
            b		mtspr64_success              
mtspr64_hrmor:
            ld		r5,0(r4)
            mtspr	chud_970_hrmor,r5
            b		mtspr64_success  
mtspr64_hior:
            ld		r5,0(r4)
            mtspr	chud_970_hior,r5
            b		mtspr64_success  
mtspr64_lpidr:
            ld		r5,0(r4)
            mtspr	chud_970_lpidr,r5
            b		mtspr64_success   
mtspr64_lpcr:
            ld		r5,0(r4)
            mtspr	chud_970_lpcr,r5
            b		mtspr64_success    
mtspr64_dabrx:
            ld		r5,0(r4)
            mtspr	chud_970_dabrx,r5
            b		mtspr64_success    
mtspr64_hsprg0:
            ld		r5,0(r4)
            mtspr	chud_970_hsprg0,r5
            b		mtspr64_success   
mtspr64_hsprg1:
            ld		r5,0(r4)
            mtspr	chud_970_hsprg1,r5
            b		mtspr64_success 
mtspr64_hsrr0:
            ld		r5,0(r4)
            mtspr	chud_970_hsrr0,r5
            b		mtspr64_success 
mtspr64_hsrr1:
            ld		r5,0(r4)
            mtspr	chud_970_hsrr1,r5
            b		mtspr64_success 
mtspr64_hdec:
            ld		r5,0(r4)
            mtspr	chud_970_hdec,r5
            b		mtspr64_success             
mtspr64_trig0:
            ld		r5,0(r4)
            mtspr	chud_970_trig0,r5
            b		mtspr64_success 
mtspr64_trig1:
            ld		r5,0(r4)
            mtspr	chud_970_trig1,r5
            b		mtspr64_success
mtspr64_trig2:
            ld		r5,0(r4)
            mtspr	chud_970_trig2,r5
            b		mtspr64_success
mtspr64_accr:
            ld		r5,0(r4)
            mtspr	chud_ppc64_accr,r5
            b		mtspr64_success
mtspr64_scomc:
            ld		r5,0(r4)
            mtspr	chud_970_scomc,r5
            b		mtspr64_success
mtspr64_scomd:
            ld		r5,0(r4)
            mtspr	chud_970_scomd,r5
            b		mtspr64_success
            
mtspr64_failure:
            li		r3,KERN_FAILURE
            blr
            
mtspr64_success:
            li		r3,KERN_SUCCESS
            blr


/*
 * kern_return_t mfmsr64(uint64_t *val);
 * 
 * r3: address to store value in
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mfmsr64)

EXT(mfmsr64):            
            mfmsr	r5
            std		r5,0(r3)
mfmsr64_success:
            li		r3,KERN_SUCCESS
            blr

mfmsr64_failure:
            li		r3,KERN_FAILURE
            blr


/*
 * kern_return_t mtmsr64(uint64_t *val);
 * 
 * r3: address to load value from
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mtmsr64)

EXT(mtmsr64):            
            ld		r5,0(r3)
            mtmsrd	r5
            b		mtmsr64_success
            
mtmsr64_success:
            li		r3,KERN_SUCCESS
            blr

mtmsr64_failure:
            li		r3,KERN_FAILURE
            blr

.L_end:
Commit	Line	Data
55e303ae A	1	/*
	2	* Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
	3	*
2d21ac55	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
55e303ae	5	*
2d21ac55 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
8f6c56a5	14	*
2d21ac55 A	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5 A	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
8f6c56a5 A	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55 A	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
8f6c56a5	25	*
2d21ac55	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
55e303ae A	27	*/
55e303ae A	28
0c530ab8	29	#include <chud/ppc/chud_spr.h>
55e303ae A	30	#include <ppc/asm.h>
	31	#include <mach/kern_return.h>
	32
91447636 A	33	/*
	34	* kern_return_t mfspr64(uint64_t *val, int spr);
	35	*
	36	* r3: address to store value in
	37	* r4: spr to read from
	38	*
	39	*/
	40
	41	; Force a line boundry here
	42	.align 5
	43	.globl EXT(mfspr64)
	44
	45	EXT(mfspr64):
	46	;; generic PPC 64-bit wide SPRs
	47	cmpwi r4,chud_ppc_srr0
	48	beq mfspr64_srr0
	49	cmpwi r4,chud_ppc_srr1
	50	beq mfspr64_srr1
	51	cmpwi r4,chud_ppc_dar
	52	beq mfspr64_dar
	53	cmpwi r4,chud_ppc_sdr1
	54	beq mfspr64_sdr1
	55	cmpwi r4,chud_ppc_sprg0
	56	beq mfspr64_sprg0
	57	cmpwi r4,chud_ppc_sprg1
	58	beq mfspr64_sprg1
	59	cmpwi r4,chud_ppc_sprg2
	60	beq mfspr64_sprg2
	61	cmpwi r4,chud_ppc_sprg3
	62	beq mfspr64_sprg3
	63	cmpwi r4,chud_ppc64_asr
	64	beq mfspr64_asr
	65	cmpwi r4,chud_ppc_dabr
	66	beq mfspr64_dabr
	67
	68	;; GPUL specific 64-bit wide SPRs
	69	cmpwi r4,chud_970_hid0
	70	beq mfspr64_hid0
	71	cmpwi r4,chud_970_hid1
	72	beq mfspr64_hid1
	73	cmpwi r4,chud_970_hid4
	74	beq mfspr64_hid4
	75	cmpwi r4,chud_970_hid5
	76	beq mfspr64_hid5
	77	cmpwi r4,chud_970_mmcr0
	78	beq mfspr64_mmcr0
	79	cmpwi r4,chud_970_mmcr1
	80	beq mfspr64_mmcr1
	81	cmpwi r4,chud_970_mmcra
	82	beq mfspr64_mmcra
	83	cmpwi r4,chud_970_siar
	84	beq mfspr64_siar
	85	cmpwi r4,chud_970_sdar
	86	beq mfspr64_sdar
	87	cmpwi r4,chud_970_imc
	88	beq mfspr64_imc
	89	cmpwi r4,chud_970_rmor
	90	beq mfspr64_rmor
	91	cmpwi r4,chud_970_hrmor
	92	beq mfspr64_hrmor
	93	cmpwi r4,chud_970_hior
	94	beq mfspr64_hior
	95	cmpwi r4,chud_970_lpidr
	96	beq mfspr64_lpidr
97	cmpwi r4,chud_970_lpcr
98	beq mfspr64_lpcr
99	cmpwi r4,chud_970_dabrx
100	beq mfspr64_dabrx
101	cmpwi r4,chud_970_hsprg0
102	beq mfspr64_hsprg0
103	cmpwi r4,chud_970_hsprg1
104	beq mfspr64_hsprg1
105	cmpwi r4,chud_970_hsrr0
106	beq mfspr64_hsrr0
107	cmpwi r4,chud_970_hsrr1
108	beq mfspr64_hsrr1
109	cmpwi r4,chud_970_hdec
110	beq mfspr64_hdec
111	cmpwi r4,chud_970_trig0
112	beq mfspr64_trig0
113	cmpwi r4,chud_970_trig1
114	beq mfspr64_trig1
115	cmpwi r4,chud_970_trig2
116	beq mfspr64_trig2
117	cmpwi r4,chud_ppc64_accr
118	beq mfspr64_accr
119	cmpwi r4,chud_970_scomc
120	beq mfspr64_scomc
121	cmpwi r4,chud_970_scomd
122	beq mfspr64_scomd
123
124	b mfspr64_failure
125
126	mfspr64_srr0:
55e303ae A	127	mfspr r5,chud_ppc_srr0
55e303ae A	128	std r5,0(r3)
91447636 A	129	b mfspr64_success
91447636 A	130	mfspr64_srr1:
55e303ae A	131	mfspr r5,chud_ppc_srr1
55e303ae A	132	std r5,0(r3)
91447636 A	133	b mfspr64_success
91447636 A	134	mfspr64_dar:
55e303ae A	135	mfspr r5,chud_ppc_dar
55e303ae A	136	std r5,0(r3)
91447636 A	137	b mfspr64_success
91447636 A	138	mfspr64_sdr1:
55e303ae A	139	mfspr r5,chud_ppc_sdr1
55e303ae A	140	std r5,0(r3)
91447636 A	141	b mfspr64_success
91447636 A	142	mfspr64_sprg0:
55e303ae A	143	mfspr r5,chud_ppc_sprg0
55e303ae A	144	std r5,0(r3)
91447636 A	145	b mfspr64_success
91447636 A	146	mfspr64_sprg1:
55e303ae A	147	mfspr r5,chud_ppc_sprg1
55e303ae A	148	std r5,0(r3)
91447636 A	149	b mfspr64_success
91447636 A	150	mfspr64_sprg2:
55e303ae A	151	mfspr r5,chud_ppc_sprg2
55e303ae A	152	std r5,0(r3)
91447636 A	153	b mfspr64_success
91447636 A	154	mfspr64_sprg3:
55e303ae A	155	mfspr r5,chud_ppc_sprg3
55e303ae A	156	std r5,0(r3)
91447636 A	157	b mfspr64_success
91447636 A	158	mfspr64_asr:
55e303ae A	159	mfspr r5,chud_ppc64_asr
55e303ae A	160	std r5,0(r3)
91447636 A	161	b mfspr64_success
91447636 A	162	mfspr64_dabr:
55e303ae A	163	mfspr r5,chud_ppc_dabr
55e303ae A	164	std r5,0(r3)
91447636 A	165	b mfspr64_success
91447636 A	166	mfspr64_hid0:
55e303ae A	167	mfspr r5,chud_970_hid0
55e303ae A	168	std r5,0(r3)
91447636 A	169	b mfspr64_success
91447636 A	170	mfspr64_hid1:
55e303ae A	171	mfspr r5,chud_970_hid1
55e303ae A	172	std r5,0(r3)
91447636 A	173	b mfspr64_success
91447636 A	174	mfspr64_hid4:
55e303ae A	175	mfspr r5,chud_970_hid4
55e303ae A	176	std r5,0(r3)
91447636 A	177	b mfspr64_success
91447636 A	178	mfspr64_hid5:
55e303ae A	179	mfspr r5,chud_970_hid5
55e303ae A	180	std r5,0(r3)
91447636 A	181	b mfspr64_success
91447636 A	182	mfspr64_mmcr0:
55e303ae A	183	mfspr r5,chud_970_mmcr0
55e303ae A	184	std r5,0(r3)
91447636 A	185	b mfspr64_success
91447636 A	186	mfspr64_mmcr1:
55e303ae A	187	mfspr r5,chud_970_mmcr1
55e303ae A	188	std r5,0(r3)
91447636 A	189	b mfspr64_success
91447636 A	190	mfspr64_mmcra:
55e303ae A	191	mfspr r5,chud_970_mmcra
55e303ae A	192	std r5,0(r3)
91447636 A	193	b mfspr64_success
91447636 A	194	mfspr64_siar:
55e303ae A	195	mfspr r5,chud_970_siar
55e303ae A	196	std r5,0(r3)
91447636 A	197	b mfspr64_success
91447636 A	198	mfspr64_sdar:
55e303ae A	199	mfspr r5,chud_970_sdar
55e303ae A	200	std r5,0(r3)
91447636 A	201	b mfspr64_success
91447636 A	202	mfspr64_imc:
55e303ae A	203	mfspr r5,chud_970_imc
55e303ae A	204	std r5,0(r3)
91447636 A	205	b mfspr64_success
91447636 A	206	mfspr64_rmor:
55e303ae A	207	mfspr r5,chud_970_rmor
55e303ae A	208	std r5,0(r3)
91447636 A	209	b mfspr64_success
91447636 A	210	mfspr64_hrmor:
55e303ae A	211	mfspr r5,chud_970_hrmor
55e303ae A	212	std r5,0(r3)
91447636 A	213	b mfspr64_success
91447636 A	214	mfspr64_hior:
55e303ae A	215	mfspr r5,chud_970_hior
55e303ae A	216	std r5,0(r3)
91447636 A	217	b mfspr64_success
91447636 A	218	mfspr64_lpidr:
55e303ae A	219	mfspr r5,chud_970_lpidr
55e303ae A	220	std r5,0(r3)
91447636 A	221	b mfspr64_success
91447636 A	222	mfspr64_lpcr:
55e303ae A	223	mfspr r5,chud_970_lpcr
55e303ae A	224	std r5,0(r3)
91447636 A	225	b mfspr64_success
91447636 A	226	mfspr64_dabrx:
55e303ae A	227	mfspr r5,chud_970_dabrx
55e303ae A	228	std r5,0(r3)
91447636 A	229	b mfspr64_success
91447636 A	230	mfspr64_hsprg0:
55e303ae A	231	mfspr r5,chud_970_hsprg0
55e303ae A	232	std r5,0(r3)
91447636 A	233	b mfspr64_success
91447636 A	234	mfspr64_hsprg1:
55e303ae A	235	mfspr r5,chud_970_hsprg1
55e303ae A	236	std r5,0(r3)
91447636 A	237	b mfspr64_success
91447636 A	238	mfspr64_hsrr0:
55e303ae A	239	mfspr r5,chud_970_hsrr0
55e303ae A	240	std r5,0(r3)
91447636 A	241	b mfspr64_success
91447636 A	242	mfspr64_hsrr1:
55e303ae A	243	mfspr r5,chud_970_hsrr1
55e303ae A	244	std r5,0(r3)
91447636 A	245	b mfspr64_success
91447636 A	246	mfspr64_hdec:
55e303ae A	247	mfspr r5,chud_970_hdec
55e303ae A	248	std r5,0(r3)
91447636 A	249	b mfspr64_success
91447636 A	250	mfspr64_trig0:
55e303ae A	251	mfspr r5,chud_970_trig0
55e303ae A	252	std r5,0(r3)
91447636 A	253	b mfspr64_success
91447636 A	254	mfspr64_trig1:
55e303ae A	255	mfspr r5,chud_970_trig1
55e303ae A	256	std r5,0(r3)
91447636 A	257	b mfspr64_success
91447636 A	258	mfspr64_trig2:
55e303ae A	259	mfspr r5,chud_970_trig2
55e303ae A	260	std r5,0(r3)
91447636 A	261	b mfspr64_success
91447636 A	262	mfspr64_accr:
55e303ae A	263	mfspr r5,chud_ppc64_accr
55e303ae A	264	std r5,0(r3)
91447636 A	265	b mfspr64_success
91447636 A	266	mfspr64_scomc:
55e303ae A	267	mfspr r5,chud_970_scomc
55e303ae A	268	std r5,0(r3)
91447636 A	269	b mfspr64_success
91447636 A	270	mfspr64_scomd:
55e303ae A	271	mfspr r5,chud_970_scomd
55e303ae A	272	std r5,0(r3)
91447636 A	273	b mfspr64_success
	274
	275	mfspr64_failure:
	276	li r3,KERN_FAILURE
55e303ae A	277	blr
55e303ae A	278
91447636 A	279	mfspr64_success:
91447636 A	280	li r3,KERN_SUCCESS
55e303ae A	281	blr
55e303ae A	282
91447636 A	283
	284	/*
	285	* kern_return_t mtspr64(int spr, uint64_t *val);
	286	*
	287	* r3: spr to write to
	288	* r4: address to get value from
	289	*
	290	*/
	291
	292	; Force a line boundry here
	293	.align 5
	294	.globl EXT(mtspr64)
	295
	296	EXT(mtspr64):
	297	;; generic PPC 64-bit wide SPRs
	298	cmpwi r3,chud_ppc_srr0
	299	beq mtspr64_srr0
	300	cmpwi r3,chud_ppc_srr1
	301	beq mtspr64_srr1
	302	cmpwi r3,chud_ppc_dar
	303	beq mtspr64_dar
	304	cmpwi r3,chud_ppc_sdr1
	305	beq mtspr64_sdr1
	306	cmpwi r3,chud_ppc_sprg0
	307	beq mtspr64_sprg0
	308	cmpwi r3,chud_ppc_sprg1
	309	beq mtspr64_sprg1
	310	cmpwi r3,chud_ppc_sprg2
	311	beq mtspr64_sprg2
	312	cmpwi r3,chud_ppc_sprg3
	313	beq mtspr64_sprg3
	314	cmpwi r3,chud_ppc64_asr
	315	beq mtspr64_asr
	316	cmpwi r3,chud_ppc_dabr
	317	beq mtspr64_dabr
	318
	319	;; GPUL specific 64-bit wide SPRs
	320	cmpwi r3,chud_970_hid0
	321	beq mtspr64_hid0
	322	cmpwi r3,chud_970_hid1
	323	beq mtspr64_hid1
	324	cmpwi r3,chud_970_hid4
	325	beq mtspr64_hid4
	326	cmpwi r3,chud_970_hid5
	327	beq mtspr64_hid5
	328	cmpwi r3,chud_970_mmcr0
	329	beq mtspr64_mmcr0
	330	cmpwi r3,chud_970_mmcr1
	331	beq mtspr64_mmcr1
	332	cmpwi r3,chud_970_mmcra
	333	beq mtspr64_mmcra
	334	cmpwi r3,chud_970_siar
	335	beq mtspr64_siar
	336	cmpwi r3,chud_970_sdar
	337	beq mtspr64_sdar
	338	cmpwi r3,chud_970_imc
	339	beq mtspr64_imc
	340	cmpwi r3,chud_970_rmor
	341	beq mtspr64_rmor
	342	cmpwi r3,chud_970_hrmor
	343	beq mtspr64_hrmor
	344	cmpwi r3,chud_970_hior
	345	beq mtspr64_hior
	346	cmpwi r3,chud_970_lpidr
347	beq mtspr64_lpidr
348	cmpwi r3,chud_970_lpcr
349	beq mtspr64_lpcr
350	cmpwi r3,chud_970_dabrx
351	beq mtspr64_dabrx
352	cmpwi r3,chud_970_hsprg0
353	beq mtspr64_hsprg0
354	cmpwi r3,chud_970_hsprg1
355	beq mtspr64_hsprg1
356	cmpwi r3,chud_970_hsrr0
357	beq mtspr64_hsrr0
358	cmpwi r3,chud_970_hsrr1
359	beq mtspr64_hsrr1
360	cmpwi r3,chud_970_hdec
361	beq mtspr64_hdec
362	cmpwi r3,chud_970_trig0
363	beq mtspr64_trig0
364	cmpwi r3,chud_970_trig1
365	beq mtspr64_trig1
366	cmpwi r3,chud_970_trig2
367	beq mtspr64_trig2
368	cmpwi r3,chud_ppc64_accr
369	beq mtspr64_accr
370	cmpwi r3,chud_970_scomc
371	beq mtspr64_scomc
372	cmpwi r3,chud_970_scomd
373	beq mtspr64_scomd
374
375	b mtspr64_failure
376
377	mtspr64_srr0:
378	ld r5,0(r4)
379	mtspr chud_ppc_srr0,r5
380	b mtspr64_success
381	mtspr64_srr1:
55e303ae A	382	ld r5,0(r4)
55e303ae A	383	mtspr chud_ppc_srr1,r5
91447636 A	384	b mtspr64_success
91447636 A	385	mtspr64_dar:
55e303ae A	386	ld r5,0(r4)
55e303ae A	387	mtspr chud_ppc_dar,r5
91447636 A	388	b mtspr64_success
91447636 A	389	mtspr64_sdr1:
55e303ae A	390	ld r5,0(r4)
55e303ae A	391	mtspr chud_ppc_sdr1,r5
91447636 A	392	b mtspr64_success
91447636 A	393	mtspr64_sprg0:
55e303ae A	394	ld r5,0(r4)
55e303ae A	395	mtspr chud_ppc_sprg0,r5
91447636 A	396	b mtspr64_success
91447636 A	397	mtspr64_sprg1:
55e303ae A	398	ld r5,0(r4)
55e303ae A	399	mtspr chud_ppc_sprg1,r5
91447636 A	400	b mtspr64_success
91447636 A	401	mtspr64_sprg2:
55e303ae A	402	ld r5,0(r4)
55e303ae A	403	mtspr chud_ppc_sprg2,r5
91447636 A	404	b mtspr64_success
91447636 A	405	mtspr64_sprg3:
55e303ae A	406	ld r5,0(r4)
55e303ae A	407	mtspr chud_ppc_sprg3,r5
91447636 A	408	b mtspr64_success
91447636 A	409	mtspr64_asr:
55e303ae A	410	ld r5,0(r4)
55e303ae A	411	mtspr chud_ppc64_asr,r5
91447636 A	412	b mtspr64_success
91447636 A	413	mtspr64_dabr:
55e303ae A	414	ld r5,0(r4)
55e303ae A	415	mtspr chud_ppc_dabr,r5
91447636 A	416	b mtspr64_success
91447636 A	417	mtspr64_hid0:
55e303ae A	418	ld r5,0(r4)
	419	sync
	420	mtspr chud_970_hid0,r5
	421	mfspr r5,chud_970_hid0 /* syncronization requirements */
	422	mfspr r5,chud_970_hid0
	423	mfspr r5,chud_970_hid0
	424	mfspr r5,chud_970_hid0
	425	mfspr r5,chud_970_hid0
	426	mfspr r5,chud_970_hid0
91447636 A	427	b mtspr64_success
91447636 A	428	mtspr64_hid1:
55e303ae A	429	ld r5,0(r4)
	430	mtspr chud_970_hid1,r5 /* tell you twice */
	431	mtspr chud_970_hid1,r5
	432	isync
91447636 A	433	b mtspr64_success
91447636 A	434	mtspr64_hid4:
55e303ae A	435	ld r5,0(r4)
	436	sync /* syncronization requirements */
	437	mtspr chud_970_hid4,r5
	438	isync
91447636 A	439	b mtspr64_success
91447636 A	440	mtspr64_hid5:
55e303ae A	441	ld r5,0(r4)
55e303ae A	442	mtspr chud_970_hid5,r5
91447636 A	443	b mtspr64_success
91447636 A	444	mtspr64_mmcr0:
55e303ae A	445	ld r5,0(r4)
55e303ae A	446	mtspr chud_970_mmcr0,r5
91447636 A	447	b mtspr64_success
91447636 A	448	mtspr64_mmcr1:
55e303ae A	449	ld r5,0(r4)
55e303ae A	450	mtspr chud_970_mmcr1,r5
91447636 A	451	b mtspr64_success
91447636 A	452	mtspr64_mmcra:
55e303ae A	453	ld r5,0(r4)
55e303ae A	454	mtspr chud_970_mmcra,r5
91447636 A	455	b mtspr64_success
91447636 A	456	mtspr64_siar:
55e303ae A	457	ld r5,0(r4)
55e303ae A	458	mtspr chud_970_siar,r5
91447636 A	459	b mtspr64_success
91447636 A	460	mtspr64_sdar:
55e303ae A	461	ld r5,0(r4)
55e303ae A	462	mtspr chud_970_sdar,r5
91447636 A	463	b mtspr64_success
91447636 A	464	mtspr64_imc:
55e303ae A	465	ld r5,0(r4)
55e303ae A	466	mtspr chud_970_imc,r5
91447636 A	467	b mtspr64_success
91447636 A	468	mtspr64_rmor:
55e303ae A	469	ld r5,0(r4)
55e303ae A	470	mtspr chud_970_rmor,r5
91447636 A	471	b mtspr64_success
91447636 A	472	mtspr64_hrmor:
55e303ae A	473	ld r5,0(r4)
55e303ae A	474	mtspr chud_970_hrmor,r5
91447636 A	475	b mtspr64_success
91447636 A	476	mtspr64_hior:
55e303ae A	477	ld r5,0(r4)
55e303ae A	478	mtspr chud_970_hior,r5
91447636 A	479	b mtspr64_success
91447636 A	480	mtspr64_lpidr:
55e303ae A	481	ld r5,0(r4)
55e303ae A	482	mtspr chud_970_lpidr,r5
91447636 A	483	b mtspr64_success
91447636 A	484	mtspr64_lpcr:
55e303ae A	485	ld r5,0(r4)
55e303ae A	486	mtspr chud_970_lpcr,r5
91447636 A	487	b mtspr64_success
91447636 A	488	mtspr64_dabrx:
55e303ae	489	ld r5,0(r4)
91447636 A	490	mtspr chud_970_dabrx,r5
	491	b mtspr64_success
	492	mtspr64_hsprg0:
55e303ae A	493	ld r5,0(r4)
55e303ae A	494	mtspr chud_970_hsprg0,r5
91447636 A	495	b mtspr64_success
91447636 A	496	mtspr64_hsprg1:
55e303ae A	497	ld r5,0(r4)
55e303ae A	498	mtspr chud_970_hsprg1,r5
91447636 A	499	b mtspr64_success
91447636 A	500	mtspr64_hsrr0:
55e303ae A	501	ld r5,0(r4)
55e303ae A	502	mtspr chud_970_hsrr0,r5
91447636 A	503	b mtspr64_success
91447636 A	504	mtspr64_hsrr1:
55e303ae A	505	ld r5,0(r4)
55e303ae A	506	mtspr chud_970_hsrr1,r5
91447636 A	507	b mtspr64_success
91447636 A	508	mtspr64_hdec:
55e303ae A	509	ld r5,0(r4)
55e303ae A	510	mtspr chud_970_hdec,r5
91447636 A	511	b mtspr64_success
91447636 A	512	mtspr64_trig0:
55e303ae A	513	ld r5,0(r4)
55e303ae A	514	mtspr chud_970_trig0,r5
91447636 A	515	b mtspr64_success
91447636 A	516	mtspr64_trig1:
55e303ae A	517	ld r5,0(r4)
55e303ae A	518	mtspr chud_970_trig1,r5
91447636 A	519	b mtspr64_success
91447636 A	520	mtspr64_trig2:
55e303ae A	521	ld r5,0(r4)
55e303ae A	522	mtspr chud_970_trig2,r5
91447636 A	523	b mtspr64_success
91447636 A	524	mtspr64_accr:
55e303ae A	525	ld r5,0(r4)
55e303ae A	526	mtspr chud_ppc64_accr,r5
91447636 A	527	b mtspr64_success
91447636 A	528	mtspr64_scomc:
55e303ae A	529	ld r5,0(r4)
55e303ae A	530	mtspr chud_970_scomc,r5
91447636 A	531	b mtspr64_success
91447636 A	532	mtspr64_scomd:
55e303ae A	533	ld r5,0(r4)
55e303ae A	534	mtspr chud_970_scomd,r5
91447636 A	535	b mtspr64_success
	536
	537	mtspr64_failure:
	538	li r3,KERN_FAILURE
	539	blr
55e303ae	540
91447636 A	541	mtspr64_success:
	542	li r3,KERN_SUCCESS
	543	blr
	544
	545
	546	/*
	547	* kern_return_t mfmsr64(uint64_t *val);
	548	*
	549	* r3: address to store value in
	550	*
	551	*/
	552
	553	; Force a line boundry here
55e303ae	554	.align 5
91447636 A	555	.globl EXT(mfmsr64)
	556
	557	EXT(mfmsr64):
55e303ae A	558	mfmsr r5
55e303ae A	559	std r5,0(r3)
91447636 A	560	mfmsr64_success:
	561	li r3,KERN_SUCCESS
	562	blr
	563
	564	mfmsr64_failure:
	565	li r3,KERN_FAILURE
55e303ae A	566	blr
55e303ae A	567
91447636 A	568
	569	/*
	570	* kern_return_t mtmsr64(uint64_t *val);
	571	*
	572	* r3: address to load value from
	573	*
	574	*/
	575
	576	; Force a line boundry here
55e303ae	577	.align 5
91447636 A	578	.globl EXT(mtmsr64)
	579
	580	EXT(mtmsr64):
55e303ae A	581	ld r5,0(r3)
55e303ae A	582	mtmsrd r5
91447636 A	583	b mtmsr64_success
	584
	585	mtmsr64_success:
	586	li r3,KERN_SUCCESS
	587	blr
	588
	589	mtmsr64_failure:
	590	li r3,KERN_FAILURE
55e303ae A	591	blr
55e303ae A	592
4a249263	593	.L_end: