src/ld/dwarf2.h

   1 /*
   2  * Copyright (c) 2006 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. Please obtain a copy of the License at
  10  * http://www.opensource.apple.com/apsl/ and read it before using this
  11  * file.
  12  *
  13  * The Original Code and all software distributed under the License are
  14  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  15  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  16  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  18  * Please see the License for the specific language governing rights and
  19  * limitations under the License.
  20  *
  21  * @APPLE_LICENSE_HEADER_END@
  22  */
  23 /* These constants were taken from version 3 of the DWARF standard,
  24    which is Copyright (c) 2005 Free Standards Group, and
  25    Copyright (c) 1992, 1993 UNIX International, Inc.  */
  26
  27 #ifndef __DWARF2_H__
  28 #define __DWARF2_H__
  29
  30 /* This is not a complete list.  */
  31 enum {
  32   DW_TAG_compile_unit = 17,
  33   DW_TAG_partial_unit = 60
  34 };
  35
  36 /* This is not a complete list.  */
  37 enum {
  38   DW_AT_sibling = 1,
  39   DW_AT_name = 3,
  40   DW_AT_stmt_list = 16,
  41   DW_AT_comp_dir = 27
  42 };
  43
  44 enum {
  45   DW_FORM_addr = 1,
  46   DW_FORM_block2 = 3,
  47   DW_FORM_block4,
  48   DW_FORM_data2,
  49   DW_FORM_data4,
  50   DW_FORM_data8,
  51   DW_FORM_string,
  52   DW_FORM_block,
  53   DW_FORM_block1,
  54   DW_FORM_data1,
  55   DW_FORM_flag,
  56   DW_FORM_sdata,
  57   DW_FORM_strp,
  58   DW_FORM_udata,
  59   DW_FORM_ref_addr,
  60   DW_FORM_ref1,
  61   DW_FORM_ref2,
  62   DW_FORM_ref4,
  63   DW_FORM_ref8,
  64   DW_FORM_ref_udata,
  65   DW_FORM_indirect,
  66   /* new in Dwarf 4 */
  67   DW_FORM_sec_offset,
  68   DW_FORM_exprloc,
  69   DW_FORM_flag_present,
  70   DW_FORM_ref_sig8
  71 };
  72
  73
  74 enum {
  75   DW_LNS_extended_op = 0,
  76   DW_LNS_copy,
  77   DW_LNS_advance_pc,
  78   DW_LNS_advance_line,
  79   DW_LNS_set_file,
  80   DW_LNS_set_column,
  81   DW_LNS_negate_stmt,
  82   DW_LNS_set_basic_block,
  83   DW_LNS_const_add_pc,
  84   DW_LNS_fixed_advance_pc,
  85   DW_LNS_set_prologue_end,
  86   DW_LNS_set_epilogue_begin,
  87   DW_LNS_set_isa
  88 };
  89
  90 enum {
  91   DW_LNE_end_sequence = 1,
  92   DW_LNE_set_address,
  93   DW_LNE_define_file
  94 };
  95
  96
  97 // dwarf unwind instructions
  98 enum {
  99         DW_CFA_nop                 = 0x0,
 100         DW_CFA_set_loc             = 0x1,
 101         DW_CFA_advance_loc1        = 0x2,
 102         DW_CFA_advance_loc2        = 0x3,
 103         DW_CFA_advance_loc4        = 0x4,
 104         DW_CFA_offset_extended     = 0x5,
 105         DW_CFA_restore_extended    = 0x6,
 106         DW_CFA_undefined           = 0x7,
 107         DW_CFA_same_value          = 0x8,
 108         DW_CFA_register            = 0x9,
 109         DW_CFA_remember_state      = 0xA,
 110         DW_CFA_restore_state       = 0xB,
 111         DW_CFA_def_cfa             = 0xC,
 112         DW_CFA_def_cfa_register    = 0xD,
 113         DW_CFA_def_cfa_offset      = 0xE,
 114         DW_CFA_def_cfa_expression  = 0xF,
 115         DW_CFA_expression         = 0x10,
 116         DW_CFA_offset_extended_sf = 0x11,
 117         DW_CFA_def_cfa_sf         = 0x12,
 118         DW_CFA_def_cfa_offset_sf  = 0x13,
 119         DW_CFA_val_offset         = 0x14,
 120         DW_CFA_val_offset_sf      = 0x15,
 121         DW_CFA_val_expression     = 0x16,
 122         DW_CFA_advance_loc        = 0x40, // high 2 bits are 0x1, lower 6 bits are delta
 123         DW_CFA_offset             = 0x80, // high 2 bits are 0x2, lower 6 bits are register
 124         DW_CFA_restore            = 0xC0, // high 2 bits are 0x3, lower 6 bits are register
 125
 126         // GNU extensions
 127     DW_CFA_GNU_window_save                              = 0x2D,
 128     DW_CFA_GNU_args_size                                = 0x2E,
 129     DW_CFA_GNU_negative_offset_extended = 0x2F
 130 };
 131
 132
 133 // FSF exception handling Pointer-Encoding constants
 134 // Used in CFI augmentation by gcc compiler
 135 enum {
 136         DW_EH_PE_ptr       = 0x00,
 137         DW_EH_PE_uleb128   = 0x01,
 138         DW_EH_PE_udata2    = 0x02,
 139         DW_EH_PE_udata4    = 0x03,
 140         DW_EH_PE_udata8    = 0x04,
 141         DW_EH_PE_signed    = 0x08,
 142         DW_EH_PE_sleb128   = 0x09,
 143         DW_EH_PE_sdata2    = 0x0A,
 144         DW_EH_PE_sdata4    = 0x0B,
 145         DW_EH_PE_sdata8    = 0x0C,
 146         DW_EH_PE_absptr    = 0x00,
 147         DW_EH_PE_pcrel     = 0x10,
 148         DW_EH_PE_textrel   = 0x20,
 149         DW_EH_PE_datarel   = 0x30,
 150         DW_EH_PE_funcrel   = 0x40,
 151         DW_EH_PE_aligned   = 0x50,
 152         DW_EH_PE_indirect  = 0x80,
 153         DW_EH_PE_omit      = 0xFF
 154 };
 155
 156
 157 // DWARF  expressions
 158 enum {
 159         DW_OP_addr               = 0x03, // constant address (size target specific)
 160         DW_OP_deref              = 0x06,
 161         DW_OP_const1u            = 0x08, // 1-byte constant
 162         DW_OP_const1s            = 0x09, // 1-byte constant
 163         DW_OP_const2u            = 0x0A, // 2-byte constant
 164         DW_OP_const2s            = 0x0B, // 2-byte constant
 165         DW_OP_const4u            = 0x0C, // 4-byte constant
 166         DW_OP_const4s            = 0x0D, // 4-byte constant
 167         DW_OP_const8u            = 0x0E, // 8-byte constant
 168         DW_OP_const8s            = 0x0F, // 8-byte constant
 169         DW_OP_constu             = 0x10, // ULEB128 constant
 170         DW_OP_consts             = 0x11, // SLEB128 constant
 171         DW_OP_dup                = 0x12,
 172         DW_OP_drop               = 0x13,
 173         DW_OP_over               = 0x14,
 174         DW_OP_pick               = 0x15, // 1-byte stack index
 175         DW_OP_swap               = 0x16,
 176         DW_OP_rot                = 0x17,
 177         DW_OP_xderef             = 0x18,
 178         DW_OP_abs                = 0x19,
 179         DW_OP_and                = 0x1A,
 180         DW_OP_div                = 0x1B,
 181         DW_OP_minus              = 0x1C,
 182         DW_OP_mod                = 0x1D,
 183         DW_OP_mul                = 0x1E,
 184         DW_OP_neg                = 0x1F,
 185         DW_OP_not                = 0x20,
 186         DW_OP_or                 = 0x21,
 187         DW_OP_plus               = 0x22,
 188         DW_OP_plus_uconst        = 0x23, // ULEB128 addend
 189         DW_OP_shl                = 0x24,
 190         DW_OP_shr                = 0x25,
 191         DW_OP_shra               = 0x26,
 192         DW_OP_xor                = 0x27,
 193         DW_OP_skip               = 0x2F, // signed 2-byte constant
 194         DW_OP_bra                = 0x28, // signed 2-byte constant
 195         DW_OP_eq                 = 0x29,
 196         DW_OP_ge                 = 0x2A,
 197         DW_OP_gt                 = 0x2B,
 198         DW_OP_le                 = 0x2C,
 199         DW_OP_lt                 = 0x2D,
 200         DW_OP_ne                 = 0x2E,
 201         DW_OP_lit0               = 0x30, // Literal 0
 202         DW_OP_lit1               = 0x31, // Literal 1
 203         DW_OP_lit2               = 0x32, // Literal 2
 204         DW_OP_lit3               = 0x33, // Literal 3
 205         DW_OP_lit4               = 0x34, // Literal 4
 206         DW_OP_lit5               = 0x35, // Literal 5
 207         DW_OP_lit6               = 0x36, // Literal 6
 208         DW_OP_lit7               = 0x37, // Literal 7
 209         DW_OP_lit8               = 0x38, // Literal 8
 210         DW_OP_lit9               = 0x39, // Literal 9
 211         DW_OP_lit10              = 0x3A, // Literal 10
 212         DW_OP_lit11              = 0x3B, // Literal 11
 213         DW_OP_lit12              = 0x3C, // Literal 12
 214         DW_OP_lit13              = 0x3D, // Literal 13
 215         DW_OP_lit14              = 0x3E, // Literal 14
 216         DW_OP_lit15              = 0x3F, // Literal 15
 217         DW_OP_lit16              = 0x40, // Literal 16
 218         DW_OP_lit17              = 0x41, // Literal 17
 219         DW_OP_lit18              = 0x42, // Literal 18
 220         DW_OP_lit19              = 0x43, // Literal 19
 221         DW_OP_lit20              = 0x44, // Literal 20
 222         DW_OP_lit21              = 0x45, // Literal 21
 223         DW_OP_lit22              = 0x46, // Literal 22
 224         DW_OP_lit23              = 0x47, // Literal 23
 225         DW_OP_lit24              = 0x48, // Literal 24
 226         DW_OP_lit25              = 0x49, // Literal 25
 227         DW_OP_lit26              = 0x4A, // Literal 26
 228         DW_OP_lit27              = 0x4B, // Literal 27
 229         DW_OP_lit28              = 0x4C, // Literal 28
 230         DW_OP_lit29              = 0x4D, // Literal 29
 231         DW_OP_lit30              = 0x4E, // Literal 30
 232         DW_OP_lit31              = 0x4F, // Literal 31
 233         DW_OP_reg0               = 0x50, // Contents of reg0
 234         DW_OP_reg1               = 0x51, // Contents of reg1
 235         DW_OP_reg2               = 0x52, // Contents of reg2
 236         DW_OP_reg3               = 0x53, // Contents of reg3
 237         DW_OP_reg4               = 0x54, // Contents of reg4
 238         DW_OP_reg5               = 0x55, // Contents of reg5
 239         DW_OP_reg6               = 0x56, // Contents of reg6
 240         DW_OP_reg7               = 0x57, // Contents of reg7
 241         DW_OP_reg8               = 0x58, // Contents of reg8
 242         DW_OP_reg9               = 0x59, // Contents of reg9
 243         DW_OP_reg10              = 0x5A, // Contents of reg10
 244         DW_OP_reg11              = 0x5B, // Contents of reg11
 245         DW_OP_reg12              = 0x5C, // Contents of reg12
 246         DW_OP_reg13              = 0x5D, // Contents of reg13
 247         DW_OP_reg14              = 0x5E, // Contents of reg14
 248         DW_OP_reg15              = 0x5F, // Contents of reg15
 249         DW_OP_reg16              = 0x60, // Contents of reg16
 250         DW_OP_reg17              = 0x61, // Contents of reg17
 251         DW_OP_reg18              = 0x62, // Contents of reg18
 252         DW_OP_reg19              = 0x63, // Contents of reg19
 253         DW_OP_reg20              = 0x64, // Contents of reg20
 254         DW_OP_reg21              = 0x65, // Contents of reg21
 255         DW_OP_reg22              = 0x66, // Contents of reg22
 256         DW_OP_reg23              = 0x67, // Contents of reg23
 257         DW_OP_reg24              = 0x68, // Contents of reg24
 258         DW_OP_reg25              = 0x69, // Contents of reg25
 259         DW_OP_reg26              = 0x6A, // Contents of reg26
 260         DW_OP_reg27              = 0x6B, // Contents of reg27
 261         DW_OP_reg28              = 0x6C, // Contents of reg28
 262         DW_OP_reg29              = 0x6D, // Contents of reg29
 263         DW_OP_reg30              = 0x6E, // Contents of reg30
 264         DW_OP_reg31              = 0x6F, // Contents of reg31
 265         DW_OP_breg0              = 0x70, // base register 0 + SLEB128 offset
 266         DW_OP_breg1              = 0x71, // base register 1 + SLEB128 offset
 267         DW_OP_breg2              = 0x72, // base register 2 + SLEB128 offset
 268         DW_OP_breg3              = 0x73, // base register 3 + SLEB128 offset
 269         DW_OP_breg4              = 0x74, // base register 4 + SLEB128 offset
 270         DW_OP_breg5              = 0x75, // base register 5 + SLEB128 offset
 271         DW_OP_breg6              = 0x76, // base register 6 + SLEB128 offset
 272         DW_OP_breg7              = 0x77, // base register 7 + SLEB128 offset
 273         DW_OP_breg8              = 0x78, // base register 8 + SLEB128 offset
 274         DW_OP_breg9              = 0x79, // base register 9 + SLEB128 offset
 275         DW_OP_breg10             = 0x7A, // base register 10 + SLEB128 offset
 276         DW_OP_breg11             = 0x7B, // base register 11 + SLEB128 offset
 277         DW_OP_breg12             = 0x7C, // base register 12 + SLEB128 offset
 278         DW_OP_breg13             = 0x7D, // base register 13 + SLEB128 offset
 279         DW_OP_breg14             = 0x7E, // base register 14 + SLEB128 offset
 280         DW_OP_breg15             = 0x7F, // base register 15 + SLEB128 offset
 281         DW_OP_breg16             = 0x80, // base register 16 + SLEB128 offset
 282         DW_OP_breg17             = 0x81, // base register 17 + SLEB128 offset
 283         DW_OP_breg18             = 0x82, // base register 18 + SLEB128 offset
 284         DW_OP_breg19             = 0x83, // base register 19 + SLEB128 offset
 285         DW_OP_breg20             = 0x84, // base register 20 + SLEB128 offset
 286         DW_OP_breg21             = 0x85, // base register 21 + SLEB128 offset
 287         DW_OP_breg22             = 0x86, // base register 22 + SLEB128 offset
 288         DW_OP_breg23             = 0x87, // base register 23 + SLEB128 offset
 289         DW_OP_breg24             = 0x88, // base register 24 + SLEB128 offset
 290         DW_OP_breg25             = 0x89, // base register 25 + SLEB128 offset
 291         DW_OP_breg26             = 0x8A, // base register 26 + SLEB128 offset
 292         DW_OP_breg27             = 0x8B, // base register 27 + SLEB128 offset
 293         DW_OP_breg28             = 0x8C, // base register 28 + SLEB128 offset
 294         DW_OP_breg29             = 0x8D, // base register 29 + SLEB128 offset
 295         DW_OP_breg30             = 0x8E, // base register 30 + SLEB128 offset
 296         DW_OP_breg31             = 0x8F, // base register 31 + SLEB128 offset
 297         DW_OP_regx               = 0x90, // ULEB128 register
 298         DW_OP_fbreg              = 0x91, // SLEB128 offset
 299         DW_OP_bregx              = 0x92, // ULEB128 register followed by SLEB128 offset
 300         DW_OP_piece              = 0x93, // ULEB128 size of piece addressed
 301         DW_OP_deref_size         = 0x94, // 1-byte size of data retrieved
 302         DW_OP_xderef_size        = 0x95, // 1-byte size of data retrieved
 303         DW_OP_nop                = 0x96,
 304         DW_OP_push_object_addres = 0x97,
 305         DW_OP_call2              = 0x98, // 2-byte offset of DIE
 306         DW_OP_call4              = 0x99, // 4-byte offset of DIE
 307         DW_OP_call_ref           = 0x9A, // 4- or 8-byte offset of DIE
 308         DW_OP_lo_user            = 0xE0,
 309         DW_OP_APPLE_uninit       = 0xF0,
 310         DW_OP_hi_user            = 0xFF
 311 };
 312
 313
 314
 315 #endif