X-Git-Url: https://git.saurik.com/apple/javascriptcore.git/blobdiff_plain/a253471d7f8e4d91bf6ebabab00155c3b387d3d0..93a3786624b2768d89bfa27e46598dc64e2fb70a:/dfg/DFGFPRInfo.h?ds=sidebyside diff --git a/dfg/DFGFPRInfo.h b/dfg/DFGFPRInfo.h index 6af45dd..1d931fc 100644 --- a/dfg/DFGFPRInfo.h +++ b/dfg/DFGFPRInfo.h @@ -28,8 +28,8 @@ #if ENABLE(DFG_JIT) -#include -#include +#include "DFGRegisterBank.h" +#include "MacroAssembler.h" namespace JSC { namespace DFG { @@ -82,7 +82,7 @@ public: { ASSERT(reg != InvalidFPRReg); #if CPU(X86_64) - ASSERT(reg < 16); + ASSERT(static_cast(reg) < 16); static const char* nameForRegister[16] = { "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", @@ -90,7 +90,7 @@ public: "xmm12", "xmm13", "xmm14", "xmm15" }; #elif CPU(X86) - ASSERT(reg < 8); + ASSERT(static_cast(reg) < 8); static const char* nameForRegister[8] = { "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" @@ -102,7 +102,7 @@ public: #endif -#if CPU(ARM_THUMB2) +#if CPU(ARM) class FPRInfo { public: @@ -122,6 +122,11 @@ public: // we'll return in d0 for simplicity. static const FPRReg returnValueFPR = ARMRegisters::d0; // fpRegT0 +#if CPU(ARM_HARDFP) + static const FPRReg argumentFPR0 = ARMRegisters::d0; // fpRegT0 + static const FPRReg argumentFPR1 = ARMRegisters::d1; // fpRegT1 +#endif + // FPRReg mapping is direct, the machine regsiter numbers can // be used directly as indices into the FPR RegisterBank. COMPILE_ASSERT(ARMRegisters::d0 == 0, d0_is_0); @@ -142,15 +147,15 @@ public: static const char* debugName(FPRReg reg) { ASSERT(reg != InvalidFPRReg); - ASSERT(reg < 32); + ASSERT(static_cast(reg) < 32); static const char* nameForRegister[32] = { "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11", - "d12", "d13", "d14", "d15" - "d16", "d17", "d18", "d19" - "d20", "d21", "d22", "d23" - "d24", "d25", "d26", "d27" + "d12", "d13", "d14", "d15", + "d16", "d17", "d18", "d19", + "d20", "d21", "d22", "d23", + "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31" }; return nameForRegister[reg]; @@ -159,6 +164,163 @@ public: #endif +#if CPU(ARM64) + +class FPRInfo { +public: + typedef FPRReg RegisterType; + static const unsigned numberOfRegisters = 23; + + // Temporary registers. + // q8-q15 are callee saved, q31 is use by the MacroAssembler as fpTempRegister. + static const FPRReg fpRegT0 = ARM64Registers::q0; + static const FPRReg fpRegT1 = ARM64Registers::q1; + static const FPRReg fpRegT2 = ARM64Registers::q2; + static const FPRReg fpRegT3 = ARM64Registers::q3; + static const FPRReg fpRegT4 = ARM64Registers::q4; + static const FPRReg fpRegT5 = ARM64Registers::q5; + static const FPRReg fpRegT6 = ARM64Registers::q6; + static const FPRReg fpRegT7 = ARM64Registers::q7; + static const FPRReg fpRegT8 = ARM64Registers::q16; + static const FPRReg fpRegT9 = ARM64Registers::q17; + static const FPRReg fpRegT10 = ARM64Registers::q18; + static const FPRReg fpRegT11 = ARM64Registers::q19; + static const FPRReg fpRegT12 = ARM64Registers::q20; + static const FPRReg fpRegT13 = ARM64Registers::q21; + static const FPRReg fpRegT14 = ARM64Registers::q22; + static const FPRReg fpRegT15 = ARM64Registers::q23; + static const FPRReg fpRegT16 = ARM64Registers::q24; + static const FPRReg fpRegT17 = ARM64Registers::q25; + static const FPRReg fpRegT18 = ARM64Registers::q26; + static const FPRReg fpRegT19 = ARM64Registers::q27; + static const FPRReg fpRegT20 = ARM64Registers::q28; + static const FPRReg fpRegT21 = ARM64Registers::q29; + static const FPRReg fpRegT22 = ARM64Registers::q30; + + static const FPRReg argumentFPR0 = ARM64Registers::q0; // fpRegT0 + static const FPRReg argumentFPR1 = ARM64Registers::q1; // fpRegT1 + static const FPRReg argumentFPR2 = ARM64Registers::q2; // fpRegT2 + static const FPRReg argumentFPR3 = ARM64Registers::q3; // fpRegT3 + static const FPRReg argumentFPR4 = ARM64Registers::q4; // fpRegT4 + static const FPRReg argumentFPR5 = ARM64Registers::q5; // fpRegT5 + static const FPRReg argumentFPR6 = ARM64Registers::q6; // fpRegT6 + static const FPRReg argumentFPR7 = ARM64Registers::q7; // fpRegT7 + + static const FPRReg returnValueFPR = ARM64Registers::q0; // fpRegT0 + + static FPRReg toRegister(unsigned index) + { + ASSERT(index < numberOfRegisters); + static const FPRReg registerForIndex[numberOfRegisters] = { + fpRegT0, fpRegT1, fpRegT2, fpRegT3, fpRegT4, fpRegT5, fpRegT6, fpRegT7, + fpRegT8, fpRegT9, fpRegT10, fpRegT11, fpRegT12, fpRegT13, fpRegT14, fpRegT15, + fpRegT16, fpRegT17, fpRegT18, fpRegT19, fpRegT20, fpRegT21, fpRegT22 + }; + return registerForIndex[index]; + } + + static unsigned toIndex(FPRReg reg) + { + ASSERT(reg != InvalidFPRReg); + ASSERT(static_cast(reg) < 32); + static const unsigned indexForRegister[32] = { + 0, 1, 2, 3, 4, 5, 6, 7, + InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, InvalidIndex + }; + unsigned result = indexForRegister[reg]; + ASSERT(result != InvalidIndex); + return result; + } + + static const char* debugName(FPRReg reg) + { + ASSERT(reg != InvalidFPRReg); + ASSERT(static_cast(reg) < 32); + static const char* nameForRegister[32] = { + "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", + "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", + "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", + "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" + }; + return nameForRegister[reg]; + } + +private: + static const unsigned InvalidIndex = 0xffffffff; +}; + +#endif + +#if CPU(MIPS) + +class FPRInfo { +public: + typedef FPRReg RegisterType; + static const unsigned numberOfRegisters = 6; + + // Temporary registers. + static const FPRReg fpRegT0 = MIPSRegisters::f0; + static const FPRReg fpRegT1 = MIPSRegisters::f4; + static const FPRReg fpRegT2 = MIPSRegisters::f6; + static const FPRReg fpRegT3 = MIPSRegisters::f8; + static const FPRReg fpRegT4 = MIPSRegisters::f10; + static const FPRReg fpRegT5 = MIPSRegisters::f18; + + static const FPRReg returnValueFPR = MIPSRegisters::f0; + + static const FPRReg argumentFPR0 = MIPSRegisters::f12; + static const FPRReg argumentFPR1 = MIPSRegisters::f14; + + static FPRReg toRegister(unsigned index) + { + static const FPRReg registerForIndex[numberOfRegisters] = { + fpRegT0, fpRegT1, fpRegT2, fpRegT3, fpRegT4, fpRegT5 }; + + ASSERT(index < numberOfRegisters); + return registerForIndex[index]; + } + + static unsigned toIndex(FPRReg reg) + { + ASSERT(reg != InvalidFPRReg); + ASSERT(reg < 20); + static const unsigned indexForRegister[20] = { + 0, InvalidIndex, InvalidIndex, InvalidIndex, + 1, InvalidIndex, 2, InvalidIndex, + 3, InvalidIndex, 4, InvalidIndex, + InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, + InvalidIndex, InvalidIndex, 5, InvalidIndex, + }; + unsigned result = indexForRegister[reg]; + ASSERT(result != InvalidIndex); + return result; + } + + static const char* debugName(FPRReg reg) + { + ASSERT(reg != InvalidFPRReg); + ASSERT(reg < 32); + static const char* nameForRegister[32] = { + "f0", "f1", "f2", "f3", + "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", + "f12", "f13", "f14", "f15" + "f16", "f17", "f18", "f19" + "f20", "f21", "f22", "f23" + "f24", "f25", "f26", "f27" + "f28", "f29", "f30", "f31" + }; + return nameForRegister[reg]; + } +private: + + static const unsigned InvalidIndex = 0xffffffff; +}; + +#endif + typedef RegisterBank::iterator fpr_iterator; } } // namespace JSC::DFG