X-Git-Url: https://git.saurik.com/apple/javascriptcore.git/blobdiff_plain/93a3786624b2768d89bfa27e46598dc64e2fb70a..refs/heads/master:/dfg/DFGRegisterBank.h

diff --git a/dfg/DFGRegisterBank.h b/dfg/DFGRegisterBank.h
index 4d1be40..32c1e91 100644
--- a/dfg/DFGRegisterBank.h
+++ b/dfg/DFGRegisterBank.h
@@ -29,6 +29,8 @@
 #if ENABLE(DFG_JIT)
 
 #include "DFGCommon.h"
+#include "FPRInfo.h"
+#include "GPRInfo.h"
 
 namespace JSC { namespace DFG {
 
@@ -83,10 +85,10 @@ public:
     // returns -1 (InvalidGPRReg or InvalidFPRReg).
     RegID tryAllocate()
     {
-        VirtualRegister ignored;
+        VirtualRegister ignored = VirtualRegister();
         
         for (uint32_t i = 0; i < NUM_REGS; ++i) {
-            if (!m_data[i].lockCount && m_data[i].name == InvalidVirtualRegister)
+            if (!m_data[i].lockCount && !m_data[i].name.isValid())
                 return allocateInternal(i, ignored);
         }
         
@@ -145,7 +147,7 @@ public:
 
         ++m_data[index].lockCount;
         VirtualRegister name = nameAtIndex(index);
-        if (name != InvalidVirtualRegister)
+        if (name.isValid())
             releaseAtIndex(index);
         
         return name;
@@ -163,8 +165,8 @@ public:
         ASSERT(index < NUM_REGS);
         ASSERT(m_data[index].lockCount);
         // 'index' should not currently be named, the new name must be valid.
-        ASSERT(m_data[index].name == InvalidVirtualRegister);
-        ASSERT(name != InvalidVirtualRegister);
+        ASSERT(!m_data[index].name.isValid());
+        ASSERT(name.isValid());
         // 'index' should not currently have a spillOrder.
         ASSERT(m_data[index].spillOrder == SpillHintInvalid);
 
@@ -199,7 +201,7 @@ public:
     }
 
     // Get the name (VirtualRegister) associated with the
-    // given register (or InvalidVirtualRegister for none).
+    // given register (or default VirtualRegister() for none).
     VirtualRegister name(RegID reg) const
     {
         return nameAtIndex(BankInfo::toIndex(reg));
@@ -207,22 +209,20 @@ public:
     
     bool isInUse(RegID reg) const
     {
-        return isLocked(reg) || name(reg) != InvalidVirtualRegister;
+        return isLocked(reg) || name(reg).isValid();
     }
     
-#ifndef NDEBUG
     void dump()
     {
         // For each register, print the VirtualRegister 'name'.
         for (uint32_t i =0; i < NUM_REGS; ++i) {
-            if (m_data[i].name != InvalidVirtualRegister)
-                dataLogF("[%02d]", m_data[i].name);
+            if (m_data[i].name.isValid())
+                dataLogF("[%02d]", m_data[i].name.offset());
             else
                 dataLogF("[--]");
         }
         dataLogF("\n");
     }
-#endif
 
     class iterator {
     friend class RegisterBank<BankInfo>;
@@ -310,11 +310,11 @@ private:
         // 'index' must be a valid register.
         ASSERT(index < NUM_REGS);
         // 'index' should currently be named.
-        ASSERT(m_data[index].name != InvalidVirtualRegister);
+        ASSERT(m_data[index].name.isValid());
         // 'index' should currently have a valid spill order.
         ASSERT(m_data[index].spillOrder != SpillHintInvalid);
 
-        m_data[index].name = InvalidVirtualRegister;
+        m_data[index].name = VirtualRegister();
         m_data[index].spillOrder = SpillHintInvalid;
     }
 
@@ -325,7 +325,7 @@ private:
         ASSERT(i < NUM_REGS && !m_data[i].lockCount);
 
         // Return the VirtualRegister of the named value currently stored in
-        // the register being returned - or InvalidVirtualRegister if none.
+        // the register being returned - or default VirtualRegister() if none.
         spillMe = m_data[i].name;
 
         // Clear any name/spillOrder currently associated with the register,
@@ -343,7 +343,7 @@ private:
     // count, name and spillOrder hint.
     struct MapEntry {
         MapEntry()
-            : name(InvalidVirtualRegister)
+            : name(VirtualRegister())
             , spillOrder(SpillHintInvalid)
             , lockCount(0)
         {
@@ -358,6 +358,9 @@ private:
     MapEntry m_data[NUM_REGS];
 };
 
+typedef RegisterBank<GPRInfo>::iterator gpr_iterator;
+typedef RegisterBank<FPRInfo>::iterator fpr_iterator;
+
 } } // namespace JSC::DFG
 
 #endif